STM32F100V6T7BTR データシートの表示（PDF） - STMicroelectronics

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STM32F100V6T7BTR

Low & medium-density value line, advanced ARM®-based 32-bit MCU with 16 to 128 KB Flash, 12 timers, ADC, DAC & 8 comm interfaces

STMicroelectronics 

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Electrical characteristics

5.3.18 DAC electrical specifications

Symbol

Table 46. DAC characteristics

Parameter

Min Typ

Max(1)

Unit

Comments

VDDA

Analog supply voltage

2.4 -

3.6

V-

VREF+

VSSA

RLOAD(2)

RO(1)

Reference supply voltage

Ground

Resistive load with buffer ON

Impedance output with buffer

OFF

2.4 -

0-

5-

-

-

3.6

V

VREF+ must always be below

VDDA

0

V-

-

kΩ -

When the buffer is OFF, the

15

kΩ

Minimum resistive load between

DAC_OUT and VSS to have a

1% accuracy is 1.5 MΩ

CLOAD(1)

Capacitive load

-

-

Maximum capacitive load at

50

pF DAC_OUT pin (when the buffer

is ON).

DAC_OUT Lower DAC_OUT voltage with

min(1)

buffer ON

DAC_OUT Higher DAC_OUT voltage with

max(1)

buffer ON

DAC_OUT Lower DAC_OUT voltage with

min(1)

buffer OFF

DAC_OUT Higher DAC_OUT voltage with

max(1)

buffer OFF

It gives the maximum output

0.2 -

-

V excursion of the DAC.

It corresponds to 12-bit input

code (0x0E0) to (0xF1C) at

-

-

VDDA – 0.2

V

VREF+ = 3.6 V and (0x155) and

(0xEAB) at VREF+ = 2.4 V

- 0.5

-

mV

It gives the maximum output

-

-

VREF+ –

1LSB

excursion of the DAC.

V

IDDVREF+

DAC DC current consumption in

quiescent mode (Standby mode)

-

-

With no load, worst code

220

µA

(0xF1C) at VREF+ = 3.6 V in

terms of DC consumption on the

inputs

-

-

380

µA

With no load, middle code

(0x800) on the inputs

IDDA

DAC DC current consumption in

quiescent mode (Standby mode)

-

-

With no load, worst code

480

µA

(0xF1C) at VREF+ = 3.6 V in

terms of DC consumption on the

inputs

DNL(1)

INL(1)

Differential non linearity

Difference between two

consecutive code-1LSB)

-

-

-

-

Integral non linearity (difference

between measured value at

-

-

Code i and the value at Code i

on a line drawn between Code 0 -

-

and last Code 1023)

±0.5

LSB

Given for the DAC in 10-bit

configuration

±2

LSB

Given for the DAC in 12-bit

configuration

±1

LSB

Given for the DAC in 10-bit

configuration

±4

LSB

Given for the DAC in 12-bit

configuration

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