STM32F100RBH7B データシートの表示（PDF） - STMicroelectronics

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STM32F100RBH7B

Low & medium-density value line, advanced ARM®-based 32-bit MCU with 16 to 128 KB Flash, 12 timers, ADC, DAC & 8 comm interfaces

STMicroelectronics 

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

Symbol

Table 46. DAC characteristics (continued)

Parameter

Min Typ

Max(1)

Unit

Comments

Offset error

-

-

Offset(1)

(difference between measured

value at Code (0x800) and the

-

-

ideal value = VREF+/2)

-

-

Gain

error(1)

Gain error

-

-

Settling time (full scale: for a 10-

bit input code transition between

tSETTLING(1) the lowest and the highest input -

3

codes when DAC_OUT reaches

final value ±1LSB

Update

rate(1)

Max frequency for a correct

DAC_OUT change when small

variation in the input code (from

-

-

code i to i+1LSB)

tWAKEUP(1)

Wakeup time from off state

(Setting the ENx bit in the DAC

Control register)

- 6.5

±10

mV

Given for the DAC in 12-bit

configuration

±3

LSB

Given for the DAC in 10-bit at

VREF+ = 3.6 V

±12

LSB

Given for the DAC in 12-bit at

VREF+ = 3.6 V

±0.5

%

Given for the DAC in 12bit

configuration

4

µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

1

MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

10

µs input code between lowest and

highest possible ones.

PSRR+ (1)

Power supply rejection ratio (to

VDDA) (static DC measurement

- –67

–40

dB No RLOAD, CLOAD = 50 pF

1. Guaranteed by characterization results.

2. Guaranteed by design.

Figure 36. 12-bit buffered /non-buffered DAC

Buffered/Non-buffered DAC

12-bit

digital to

analog

converter

Buffer(1)

RL

DAC_OUTx

CL

ai17157V2

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external

loads directly without the use of an external operational amplifier. The buffer can be bypassed by

configuring the BOFFx bit in the DAC_CR register.

74/96

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