DHQ1ECCSECETS1SR1WH データシートの表示（PDF） - Intel

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DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

21.8

21.8.1

21.8.1.1

21.8.1.2

21.8.1.3

21.8.2

21.8.2.1

8254 Programmable Interval Timer

The 8254 contains three counters which have fixed uses. All registers are in the core

well and clocked by a 14.31818 MHz clock.

Features

Counter 0, System Timer

This counter functions as the system timer by controlling the state of IRQ0 and is

programmed for Mode 3 operation. The counter produces a square wave with a period

equal to the product of the counter period (838 ns) and the initial count value. The

counter loads the initial count value one counter period after software writes the count

value to the counter I/O address. The counter initially asserts IRQ0 and decrements the

count value by two, each counter period. The counter negates IRQ0 when the count

value reaches 0. It then reloads the initial count value and again decrements the initial

count value by two, each counter period. The counter then asserts IRQ0 when the

count value reaches 0, reloads the initial count value, and repeats the cycle, alternately

asserting and negating IRQ0.

Counter 1, Refresh Request Signal

This counter is programmed for Mode 2 operation and impacts the period of the

NSC.RTS (NMI Status and Control Register, bit4, Refresh Cycle Toggle Status).

Programming the counter to anything other than Mode 2 results in undefined behavior.

Counter 2, Speaker Tone

This counter is typically programmed for Mode 3 operation.

Use

Timer Programming

The counter/timers are programmed in the following fashion:

• Write a control word to select a counter

• Write an initial count for that counter.

• Load the least and/or most significant bytes (as required by Control Word bits 5, 4)

of the 16-bit counter.

• Repeat with other counters

Only two conventions must be observed when programming the counters. First, for

each counter, the control word must be written before the initial count is written.

Second, the initial count must follow the count format specified in the control word

(least significant byte only, most significant byte only, or least significant byte and then

most significant byte).

A new initial count may be written to a counter at any time without affecting the

counter's programmed mode. Counting will be affected as described in the mode

definitions. The new count must follow the programmed count format.

If a counter is programmed to read/write two-byte counts, the following precaution

applies: A program must not transfer control between writing the first and second byte

to another routine which also writes into that same counter. Otherwise, the counter will

be loaded with an incorrect count.

Intel® Quark SoC X1000

DS

858

October 2013

Document Number: 329676-001US

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