DHQ1ECCSECETS1SR1WH データシートの表示（PDF） - Intel

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DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Intel® Quark SoC X1000—Legacy Bridge

interrupt entered with the interrupt acknowledge. When the PIC is operated in modes

that preserve the fully nested structure, software can determine which ISR bit to clear

by issuing a Specific EOI.

An ISR bit that is masked is not cleared by a Non-Specific EOI if the PIC is in the special

mask mode. An EOI command must be issued for both the master and slave controller.

21.12.1.4.9 Automatic End of Interrupt Mode

In this mode, the PIC automatically performs a Non-Specific EOI operation at the

trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this

mode should be used only when a nested multi-level interrupt structure is not required

within a single PIC. The AEOI mode can only be used in the master controller and not

the slave controller.

Note:

Both the master and slave PICs have an AEOI bit: MICW4.AEOI and SICW4.AEOI

respectively. Only the MICW4.AEOI bit should be set by software. The SICW4.AEOI bit

should not be set by software.

21.12.1.5 Masking Interrupts

21.12.1.5.1 Masking on an Individual Interrupt Request

Each interrupt request can be masked individually by the Interrupt Mask Register

(IMR). This register is programmed through OCW1. Each bit in the IMR masks one

interrupt channel. Masking IRQ2 on the master controller masks all requests for service

from the slave controller.

21.12.1.5.2 Special Mask Mode

Some applications may require an interrupt service routine to dynamically alter the

system priority structure during its execution under software control. For example, the

routine may wish to inhibit lower priority requests for a portion of its execution but

enable some of them for another portion.

The special mask mode enables all interrupts not masked by a bit set in the Mask

register. Normally, when an interrupt service routine acknowledges an interrupt without

issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower priority

requests. In the special mask mode, any interrupts may be selectively enabled by

loading the Mask Register with the appropriate pattern.

The special mask mode is set by OCW3.ESMM=1b & OCW3.SMM=1b, and cleared

where OCW3.ESMM=1b & OCW3.SMM=0b.

21.12.1.6 Steering of PCI Interrupts

The SoC can be programmed to allow PIRQ[A:H]# to be internally routed to interrupts

3-7, 9-12, 14 or 15, through the PIRQx Route Control registers in Device 31:Function

0. One or more PIRQx# lines can be routed to the same IRQx input. The PIRQx# lines

are defined as active low, level sensitive. When a PIRQx# is routed to specified IRQ

line, software must change the corresponding ELCR1 or ELCR2 register to level

sensitive mode. The SoC will internally invert the PIRQx# line to send an active high

level to the PIC. When a PCI interrupt is routed onto the PIC, the selected IRQ can no

longer be used by an ISA device

21.12.2

Register Map

See Chapter 5.0, “Register Access Methods” for additional information.

Intel® Quark SoC X1000

DS

890

October 2013

Document Number: 329676-001US

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