AT90PWM2B-16SU データシートの表示（PDF） - Atmel Corporation

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AT90PWM2B-16SU

8-bit Atmel Microcontroller with 8K Bytes In-System Programmable Flash

Atmel Corporation 

AT90PWM2/3/2B/3B

• Bit 1 – U2X: Double the USART Transmission Speed

This bit only has effect for the asynchronous operation. Write this bit to zero when using syn-

chronous operation.

Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou-

bling the transfer rate for asynchronous communication.

This bit is available in both USART and EUSART modes.

• Bit 0 – MPCM: Multi-processor Communication Mode

This bit enables the Multi-processor Communication mode. When the MPCM bit is written to

one, all the incoming frames received by the USART Receiver that do not contain address infor-

mation will be ignored. The Transmitter is unaffected by the MPCM setting. For more detailed

information see “Multi-processor Communication Mode” on page 202.

This mode is unavailable when the EUSART mode is set.

18.10.3

USART Control and Status Register B – UCSRB

Bit

Read/Write

Initial Value

7

RXCIE

R/W

0

6

TXCIE

R/W

0

5

UDRIE

R/W

0

4

RXEN

R/W

0

3

TXEN

R/W

0

2

UCSZ2

R/W

0

1

RXB8

R

0

0

TXB8

R/W

0

UCSRB

• Bit 7 – RXCIE: RX Complete Interrupt Enable

Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt

will be generated only if the RXCIE bit is written to one, the Global Interrupt Flag in SREG is writ-

ten to one and the RXC bit in UCSRA is set.

This bit is available for both USART and EUSART modes.

• Bit 6 – TXCIE: TX Complete Interrupt Enable

Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt

will be generated only if the TXCIE bit is written to one, the Global Interrupt Flag in SREG is writ-

ten to one and the TXC bit in UCSRA is set.

This bit is available for both USART and EUSART mode.

• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable

Writing this bit to one enables interrupt on the UDRE flag. A Data Register Empty interrupt will

be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written

to one and the UDRE bit in UCSRA is set.

This bit is available for both USART and EUSART mode.

• Bit 4 – RXEN: Receiver Enable

Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper-

ation for the RxD pin when enabled. Disabling the Receiver will flush the receive buffer

invalidating the FE, DOR, and UPE Flags.

This bit is available for both USART and EUSART mode.

• Bit 3 – TXEN: Transmitter Enable

Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port

operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXEN to

zero) will not become effective until ongoing and pending transmissions are completed, i.e.,

4317K–AVR–03/2013

205

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