AT90PWM2/3/2B/3B
Table 7-9. Start-up Times when the PLL is selected as system clock
CKSEL
3..0
SUT1..0
00
Start-up Time from Power-down
and Power-save
1K CK
Additional Delay from Reset
(VCC = 5.0V)
14CK
0101
01
Ext Osc
10
1K CK
16K CK
14CK + 4 ms
14CK + 4 ms
11
00
0001
01
Ext Clk
10
16K CK
6 CK (1)
6 CK (2)
6 CK (3)
14CK + 64 ms
14CK
14CK + 4 ms
14CK + 64 ms
11
Reserved
1.
This value do not provide a proper restart ; do not use PD in this clock scheme
2.
This value do not provide a proper restart ; do not use PD in this clock scheme
3.
This value do not provide a proper restart ; do not use PD in this clock scheme
Figure 7-4. PCK Clocking System AT90PWM2/3
OSCCAL
PLLE
PLLF
Lock
Detector
RC OSCILLATOR 8 MHz
DIVIDE
PLL
BY 8
64x
XTAL1
XTAL2
OSCILLATORS
DIVIDE
BY 2
DIVIDE
BY 4
PLOCK
CLK PLL
CK SOURCE
36
4317K–AVR–03/2013