DSPIC33FJ64GP706AI/PF データシートの表示（PDF） - Microchip Technology

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DSPIC33FJ64GP706AI/PF

High-Performance, 16-Bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJXXXGPX06A/X08A/X10A

FIGURE 25-22: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS

BIT_CLK

(CSCK)

CS61

CS60

CS62

CS21

CS20

SYNC

(COFS)

CS80

LSb

SDOx

(CSDO)

MSb

SDIx

(CSDI)

MSb In

CS65 CS66

CS71

CS72

CS76

CS70

CS76

CS75

CS75

LSb

TABLE 25-39: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤TA ≤+85°C

-40°C ≤TA ≤+125°C for Extended

Param

No.

Symbol

Characteristic(1,2)

Min Typ(3) Max Units

Conditions

CS60 TBCLKL BIT_CLK Low Time

36 40.7 45

ns

—

CS61 TBCLKH BIT_CLK High Time

36 40.7 45

ns

—

CS62 TBCLK BIT_CLK Period

— 81.4 —

ns Bit clock is input

CS65 TSACL Input Setup Time to

—

—

10

ns

—

Falling Edge of BIT_CLK

CS66 THACL Input Hold Time from

—

—

10

ns

—

Falling Edge of BIT_CLK

CS70 TSYNCLO SYNC Data Output Low Time

— 19.5 —

μs Note 1

CS71 TSYNCHI SYNC Data Output High Time

—

1.3 —

μs Note 1

CS72 TSYNC SYNC Data Output Period

— 20.8 —

μs Note 1

CS75 TRACL Rise Time, SYNC, SDATA_OUT —

10

25

ns CLOAD = 50 pF, VDD = 5V

CS76 TFACL Fall Time, SYNC, SDATA_OUT

—

10

25

ns CLOAD = 50 pF, VDD = 5V

CS77 TRACL Rise Time, SYNC, SDATA_OUT —

—

30

ns CLOAD = 50 pF, VDD = 3V

CS78 TFACL Fall Time, SYNC, SDATA_OUT

—

—

30

ns CLOAD = 50 pF, VDD = 3V

CS80 TOVDACL Output Valid Delay from Rising

—

—

15

ns

—

Edge of BIT_CLK

Note 1: These parameters are characterized but not tested in manufacturing.

2: These values assume BIT_CLK frequency is 12.288 MHz.

3: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

© 2011 Microchip Technology Inc.

DS70593C-page 309

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