STM32F091VCY6TR データシートの表示（PDF） - STMicroelectronics

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STM32F091VCY6TR

ARM®-based 32-bit MCU, up to 256 KB Flash, CAN, 12 timers, ADC, DAC, and comm. interfaces, 2.0 - 3.6V

STMicroelectronics 

Electrical characteristics

STM32F091xB STM32F091xC

Table 50. ESD absolute maximum ratings

Symbol

Ratings

Conditions

Packages

VESD(HBM)

Electrostatic discharge voltage

(human body model)

TA = +25 °C, conforming

to JESD22-A114

All

VESD(CDM)

Electrostatic discharge voltage

(charge device model)

TA = +25 °C, conforming

to ANSI/ESD STM5.3.1

WLCSP64,

LQFP100

All others

1. Data based on characterization results, not tested in production.

Class

2

C3

C4

Maximum

value(1)

2000

250

500

Unit

V

V

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up

performance:

• A supply overvoltage is applied to each power supply pin.

• A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 51. Electrical sensitivities

Symbol

Parameter

Conditions

LU

Static latch-up class TA = +105 °C conforming to JESD78A

Class

II level A

6.3.13

I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or

above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal

product operation. However, in order to give an indication of the robustness of the

microcontroller in cases when abnormal injection accidentally happens, susceptibility tests

are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting

current into the I/O pins programmed in floating input mode. While current is injected into

the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher

than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out

of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or

oscillator frequency deviation).

The characterization results are given in Table 52.

Negative induced leakage current is caused by negative injection and positive induced

leakage current is caused by positive injection.

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