STM32F091VCY6TR データシートの表示（PDF） - STMicroelectronics
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STM32F091VCY6TR
STMicroelectronics
STM32F091VCY6TR Datasheet PDF : 128 Pages
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Electrical characteristics
STM32F091xB STM32F091xC
Table 57. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fTRIG(2)
External trigger frequency
fADC = 14 MHz,
12-bit resolution
-
12-bit resolution
-
VAIN
Conversion voltage range
-
0
RAIN(2)
External input impedance
See Equation 1 and
Table 58 for details
-
RADC(2)
Sampling switch
resistance
-
-
-
823
kHz
-
17
1/fADC
-
VDDA
V
-
50
kΩ
-
1
kΩ
CADC(2)
Internal sample and hold
capacitor
-
-
-
8
pF
tCAL(2)(3)
Calibration time
WLATENCY(2)(4)
ADC_DR register ready
latency
fADC = 14 MHz
-
ADC clock = HSI14
ADC clock = PCLK/2
5.9
µs
83
1/fADC
1.5 ADC
1.5 ADC
cycles + 2
- cycles + 3
-
fPCLK cycles
fPCLK cycles
-
4.5
-
fPCLK
cycle
ADC clock = PCLK/4
-
8.5
-
fPCLK
cycle
tlatr(2)
JitterADC
fADC = fPCLK/2 = 14 MHz
fADC = fPCLK/2
Trigger conversion latency fADC = fPCLK/4 = 12 MHz
fADC = fPCLK/4
fADC = fHSI14 = 14 MHz
ADC jitter on trigger
conversion
fADC = fHSI14
0.179
-
0.196
5.5
0.219
10.5
-
1
0.250
-
µs
1/fPCLK
µs
1/fPCLK
µs
1/fHSI14
tS(2)
tSTAB(2)
Sampling time
Stabilization time
tCONV(2)
Total conversion time
(including sampling time)
fADC = 14 MHz
-
-
fADC = 14 MHz,
12-bit resolution
12-bit resolution
0.107
-
1.5
-
14
1
-
17.1
239.5
18
µs
1/fADC
1/fADC
µs
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1.
During
on IDD
conversion of the sampled value
should be taken into account.
(12.5
x
ADC
clock
period),
an
additional
consumption
of
100
µA
on
IDDA
and
60
µA
2. Guaranteed by design, not tested in production.
3. Specified value includes only ADC timing. It does not include the latency of the register access.
4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.
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DocID026284 Rev 4
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