STM32L152VCT6DTR データシートの表示（PDF） - STMicroelectronics
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STM32L152VCT6DTR
STMicroelectronics
STM32L152VCT6DTR Datasheet PDF : 136 Pages
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Electrical characteristics
STM32L151xC STM32L152xC
Note:
1. Guaranteed by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
I2S characteristics
Table 54. I2S characteristics
Symbol
Parameter
Conditions
Min
Max Unit
fMCK
fCK
I2S Main Clock Output
I2S clock frequency
Master data: 32 bits
Slave data: 32 bits
256 x 8K 256xFs (1) MHz
-
64xFs
MHz
-
64xFs
DCK I2S clock frequency duty cycle Slave receiver, 48KHz
30
tr(CK)
tf(CK)
I2S clock rise time
I2S clock fall time
Capacitive load CL=30pF
-
tv(WS) WS valid time
Master mode
4
th(WS) WS hold time
Master mode
0
tsu(WS) WS setup time
Slave mode
15
th(WS) WS hold time
Slave mode
0
tsu(SD_MR) Data input setup time
Master receiver
8
tsu(SD_SR) Data input setup time
Slave receiver
9
th(SD_MR) Data input hold time
Master receiver
5
th(SD_SR)
Slave receiver
4
tv(SD_ST) Data output valid time
Slave transmitter
(after enable edge)
-
70
%
8
8
24
-
-
-
-
-
-
ns
-
64
th(SD_ST) Data output hold time
Slave transmitter
(after enable edge)
22
-
tv(SD_MT) Data output valid time
Master transmitter
(after enable edge)
-
12
th(SD_MT) Data output hold time
Master transmitter
(after enable edge)
8
-
1. The maximum for 256xFs is 8 MHz
Refer to the I2S section of the product reference manual for more details about the sampling
frequency (Fs), fMCK, fCK and DCK values. These values reflect only the digital peripheral
behavior, source clock precision might slightly change them. DCK depends mainly on the
ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of
(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.
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DocID022799 Rev 13
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