R5F10367GSP-W0 データシートの表示（PDF） - Renesas Electronics

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R5F10367GSP-W0

RENESAS MCU True Low Power Platform (as low as 63 μA/MHz), 1.8V to 5.5V operation, 2 to 16 Kbyte Flash, 31 DMIPS at 24MHz, for General Purpose Applications

Renesas Electronics 

RL78/G12

2. ELECTRICAL SPECIFICATIONS (A, D: TA = −40 to +85°C)

<R> (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode)

(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed

main) Mode

MIN.

MAX.

SCLr clock frequency

fSCL

4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 kΩ

400Note1

2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 kΩ

400Note1

1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2

300Note1

Cb = 100 pF, Rb = 5.5 kΩ

Hold time when SCLr = “L” tLOW

4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 kΩ

1150

2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 kΩ

1150

1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2 1550

Cb = 100 pF, Rb = 5.5 kΩ

Hold time when SCLr = “H” tHIGH

4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

675

Cb = 100 pF, Rb = 2.8 kΩ

2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

600

Cb = 100 pF, Rb = 2.7 kΩ

1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2

610

Cb = 100 pF, Rb = 5.5 kΩ

Data setup time (reception) tSU:DAT

4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 kΩ

1/fMCK

+ 190

Note3

LS (low-speed

Unit

main) Mode

MIN.

MAX.

300Note1 kHz

300Note1 kHz

300Note1 kHz

1550

ns

1550

ns

1550

ns

610

ns

610

ns

610

ns

1/fMCK

ns

+ 190

Note3

2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

1/fMCK

1/fMCK

ns

Cb = 100 pF, Rb = 2.7 kΩ

+ 190

+ 190

Note3

Note3

1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2 1/fMCK

1/fMCK

ns

Cb = 100 pF, Rb = 5.5 kΩ

+ 190

Note3

+ 190

Note3

Data hold time

(transmission)

tHD:DAT

4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 kΩ

0

355

0

355

ns

2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 kΩ

0

355

0

355

ns

1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2

0

405

0

405

ns

Cb = 100 pF, Rb = 5.5 kΩ

<R> Notes 1. The value must also be equal to or less than fMCK/4.

2. Use it with VDD ≥ Vb.

3. Set tSU:DAT so that it will not exceed the hold time when SCLr = "L" or SCLr = "H".

<R> Cautions 1. Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin

and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode

register 1 (PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC

characteristics with TTL input buffer selected.

2. IIC01 and IIC11 cannot communicate at different potential.

(Remarks are listed on the next page.)

R01DS0193EJ0200 Rev.2.00

Sep 06, 2013

Page 50 of 106

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