DSPIC33FJ16GS204-I/SP データシートの表示（PDF） - Microchip Technology

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DSPIC33FJ16GS204-I/SP

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

REGISTER 8-3:

U-0

—

bit 15

PLLFBD: PLL FEEDBACK DIVISOR REGISTER

U-0

U-0

U-0

U-0

U-0

—

—

—

—

—

U-0

R/W-0

—

PLLDIV<8>

bit 8

R/W-0

bit 7

R/W-0

R/W-1

R/W-1

R/W-0

PLLDIV<7:0>

R/W-0

R/W-0

R/W-0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-9

bit 8-0

Unimplemented: Read as ‘0’

PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)

000000000 = 2

000000001 = 3

000000010 = 4

•

•

•

000110000 = 50 (default)

•

•

•

111111111 = 513

© 2009 Microchip Technology Inc.

Preliminary

DS70318D-page 141

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