STM8AP6228UAX データシートの表示（PDF） - STMicroelectronics
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STM8AP6228UAX
STMicroelectronics
STM8AP6228UAX Datasheet PDF : 89 Pages
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STM8AF61xx, STM8AF62xx
9
Option bytes
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Each option
byte has to be stored twice, for redundancy, in a regular form (OPTx) and a complemented
one (NOPTx), except for the ROP (read-out protection) option byte and option bytes 8 to 16.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 17: Option bytes below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the
ROP and UBC options that can only be toggled in ICP mode (via SWIM).
Refer to the STM8 Flash programming manual (PM0051) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Table 17. Option bytes
Addr.
Option Option
name byte no.
7
6
5
Option bits
4
3
2
Factory
default
1
0 setting
0x00
4800
Read-out
protection
(ROP)
OPT0
ROP[7:0]
0x00
0x00
4801
0x00
4802
User boot
code
(UBC)
OPT1
NOPT1
Reserved
Reserved
UBC[5:0]
NUBC[5:0]
0x00
0xFF
0x00
4803
0x00
4804
Alternate
function
remapping
(AFR)
OPT2
NOPT2
AFR7
NAFR
7
AFR6
NAFR
6
AFR5
NAFR
5
AFR4
NAFR
4
AFR3
NAFR
3
AFR2
NAFR
2
AFR1 AFR0
NAFR NAFR
1
0
0x00
0xFF
0x00
4805
0x00
4806
Watchdog
option
OPT3
NOPT3
Reserved
Reserved
16MHZ LSI
TRIM0 _EN
N16MHZ NLSI
TRIM0 _EN
IWDG WWDG WWDG
_HW _HW _HALT
NIWDG NWWD NWWG
_HW G_HW _HALT
0x00
0xFF
0x00
4807
0x00
4808
Clock
option
OPT4
NOPT4
0x00
4809
0x00
480A
HSE clock
startup
OPT5
NOPT5
Reserved
Reserved
EXT CKAWU
CLK SEL
NEXT NCKAW
CLK USEL
PRS
C1
NPR
SC1
HSECNT[7:0]
PRS
C0
NPR
SC0
0x00
0xFF
0x00
NHSECNT[7:0]
0xFF
Doc ID 14952 Rev 6
41/89
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