QL8050-6PT280M データシートの表示（PDF） - QuickLogic Corporation

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QL8050-6PT280M

Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

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TDI/RSI

Test Data In for JTAG/RAM

init. Serial Data In

TRSTB/RRO

Active low Reset for

JTAG/RAM init. reset out

Hold HIGH during normal operation. Connects to serial PROM

data in for RAM initialization. Connect to VCC if unused

Hold LOW during normal operation. Connects to serial PROM

reset for RAM initialization. Connect to GND if unused

TMS

Test Mode Select for JTAG

Hold HIGH during normal operation. Connect to VCC if not used

for JTAG

TCK

Test Clock for JTAG

Hold HIGH or LOW during normal operation. Connect to VCC or

ground if not used for JTAG

TDO/RCO

Test data out for JTAG/RAM

init. clock out

Connect to serial PROM clock for RAM initialization. Must be left

unconnected if not used for JTAG or RAM initialization

VCCIO (H)

INREF(H)

IOCTRL(H)

IO(H)

VCCIO (G)

INREF(G)

IOCTRL(G)

IO(G)

IO BANK A

IO BANK B

IO BANK F

IO BANK E

VCCIO (C)

INREF(C)

IOCTRL(C)

IO(C)

VCCIO (D)

INREF(D)

IOCTRL(D)

IO(D)

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