EP3C5E324A8ES データシートの表示（PDF） - Altera Corporation

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EP3C5E324A8ES

Cyclone III Device Handbook

Altera Corporation 

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

Phase Shift Implementation

5–23

Fine resolution phase shifts are implemented by allowing any of the output counters

(C[4..0]) or the M counter to use any of the eight phases of the VCO as the reference

clock. This allows you to adjust the delay time with a fine resolution. Equation 5–1

shows the minimum delay time that you can insert using this method.

Equation 5–1. Fine Resolution Phase Shift

fine

=

T----V----C---O--

8

=

-------1-------

8fVCO

=

--------N-----------

8MfREF

Note to Equation 5–1:

(1) fREF is the input reference clock frequency

For example, if fREF is 100 MHz, N = 1, and M = 8, then fVCO = 800 MHz, and

fine = 156.25 ps. The PLL operating frequency defines this phase shift, a value that

depends on reference clock frequency and counter settings.

Coarse resolution phase shifts are implemented by delaying the start of the counters

for a predetermined number of counter clocks. Equation 5–2 shows the coarse phase

shift.

Equation 5–2. Coarse Resolution Phase Shift

coarse

=

C------–----1--

fVCO

=

---C-----–-----1------N---

MfREF

Note to Equation 5–2:

(1) C is the count value set for the counter delay time—the initial setting in the PLL usage section of the compilation

report in the Quartus II software. If the initial value is 1, C – 1 = 0° phase shift.

July 2012 Altera Corporation

Cyclone III Device Handbook

Volume 1

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