STM32F100RCT6BTR データシートの表示（PDF） - STMicroelectronics

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STM32F100RCT6BTR

High-density value line, advanced ARM-based 32-bit MCU with 256 to 512 KB Flash, 16 timers, ADC, DAC & 11 comm interfaces

STMicroelectronics 

Electrical characteristics

STM32F100xC, STM32F100xD, STM32F100xE

Table 55. DAC characteristics (continued)

Symbol

Parameter

Min Typ Max(1) Unit

Comments

Offset(1)

Offset error

(difference between measured value

at Code (0x800) and the ideal value =

VREF+/2)

Gain

error(1)

Gain error

Settling time (full scale: for a 10-bit

input code transition between the

tSETTLING(1) lowest and the highest input codes

when DAC_OUT reaches final value

±1LSB

Update

rate(1)

Max frequency for a correct

DAC_OUT change when small

variation in the input code (from code i

to i+1LSB)

tWAKEUP(1)

Wakeup time from off state (Setting

the ENx bit in the DAC Control

register)

PSRR+ (1)

Power supply rejection ratio (to VDDA)

(static DC measurement

±10

±3

±12

±0.5

mV

Given for the DAC in 12-bit

configuration

LSB

Given for the DAC in 10-bit at

VREF+ = 3.6 V

LSB

Given for the DAC in 12-bit at

VREF+ = 3.6 V

%

Given for the DAC in 12-bit

configuration

3

4

µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

1

MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

6.5 10

–67 –40

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

µs input code between lowest and

highest possible ones.

dB No RLOAD, CLOAD = 50 pF

1. Preliminary values.

2. Quiescent mode refer to the state of the DAC keeping steady value on the output, so no dynamic consumption is involved.

Figure 37. 12-bit buffered /non-buffered DAC

Buffered/Non-buffered DAC

Buffer(1)

12-bit

digital to

analog

converter

DACx_OUT

R LOAD

C LOAD

ai17157

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly

without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the

DAC_CR register.

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Doc ID 15081 Rev 7

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