ST7FLIT15BF1BX(2007) データシートの表示（PDF） - STMicroelectronics

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ST7FLIT15BF1BX
(Rev.:2007)

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI

STMicroelectronics 

ST7LITE1xB

OPERATING CONDITIONS (Cont’d)

13.3.5.2 Devices with ‘”6” or “3” order code suffix (tested for TA = -40 to +125°C) @ VDD = 3.0 to 3.6V

Symbol

Parameter

Conditions

Min Typ Max Unit

fRC

Internal RC oscillator fre- RCCR = FF (reset value), TA=25°C, VDD= 3.3V

quency 1)

RCCR=RCCR12) ,TA=25°C,VDD= 3.3V

992

700

1000

1008

kHz

ACCRC

Accuracy of Internal RC

oscillator when calibrated

with RCCR=RCCR12)

TA=25°C,VDD=3.3V

TA=25°C,VDD=3.0 to 3.6V 3)

TA=25 to +85°C,VDD=3.3V

TA=25 to +85°C,VDD=3.0 to 3.6V 3)

TA=25 to +125°C,VDD=3.0 to 3.6V 3)

TA=-40 to +25°C,VDD=3.0 to 3.6V 3)

-0.8

+0.8 %

-1

+1 %

-3

+3 %

-3.5

+3.5 %

-5

+6.5 %

-3.5

+4 %

IDD(RC)

RC oscillator current con-

sumption

TA=25°C,VDD=3.3V

4003)

µA

tsu(RC)

fPLL

tLOCK

tSTAB

ACCPLL

tw(JIT)

JITPLL

IDD(PLL)

RC oscillator setup time

x4 PLL input clock

PLL Lock time5)

PLL Stabilization time5)

TA=25°C,VDD=3.3V

x4 PLL Accuracy

PLL jitter period 6)

fRC = 1MHz@TA=25°C, VDD=2.7 to 3.3V

fRC = 1MHz@TA=40 to +85°C, VDD= 3.3V

fRC = 1MHz

PLL jitter (∆fCPU/fCPU)

PLL current consumption TA=25°C

0.73)

102) µs

MHz

2

ms

4

ms

0.14)

%

0.14)

%

120

µs

17)

%

1903)

µA

Notes:

1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a

decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device.

2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 23.

3. Data based on characterization results, not tested in production

4. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy

5. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 13 on page 24.

6. This period is the PLL servoing period. During this period, the frequency remains unchanged.

7. Guaranteed by design.

117/157

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