PSD4202G3-90UI データシートの表示（PDF） - STMicroelectronics

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PSD4202G3-90UI

Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

STMicroelectronics 

PSD4235G2

Figure 21. Interfacing the PSD with an 80C196

80C196NT

P3.0/AD0

19 X1

P3.1/AD1

P3.2/AD2

P3.3/AD3

P3.4/AD4

18 X2

P3.5/AD5

P3.6/AD6

32

NMI

P3.7/AD7

49

6

48

VREF

VPP

ANGND

P4.0/AD8

P4.1/AD9

P4.2/AD10

P4.3/AD11

P4.4/AD12

44

45

46

47

ACH4/P0.4/PMD.0

ACH5/P0.5/PMD.1

ACH6/P0.6/PMD.2

ACH7/P0.7/PMD.3

P4.5/AD13

P4.6/AD14

P4.7/AD15

EP.0/A16

EP.1/A17

58

59

60

61

62

63

P6.0/EPA8

P6.1/EPA9

P6.2/T1CLK

P6.3/T1DIR

P6.4/SC0

64

P6.5/SD0

P6.6/SC1

65 P6.7/SD1

EP.2/A18

EP.3/A19

WR/WRL/P5.2

RD/P5.3

BHE/WRH/P5.5

ALE/ADV/P5.0

3

4

5

6

7

10

11

12

13

14

15

16

17

18

19

20

14 A16

13 A17

12 A18

11 A19

9

7

8

4

36

37

38

39

40

41

42

43

P2.0/TX/PVR

P2.1/RXD/PALE

P2.2/EXINT/PROG

P2.3/INTB

P2.4/INTINTOUT

P2.5/HLD

P2.6/HLDA/CPVER

P2.7/CLKOUT/PAC

EA 33

31

RESET

57

READY/P5.6 2

56

55

54

53

52

51

50

P1.0/EPA0/T2CLK

P1.1/EPA1

P1.2/EPA2/T2DIR

P1.3/EPA3

P1.4/EPA4

BUSWIDTH/P5.7

P1.5/EPA5

P1.6/EPA6

P1.7/EPA7

INST/P5.1

SLPINT/P5.4

10

3

1

RESET

A19-A16

AD15-AD0

VCC

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

PSD 9

3

4

5

6

7

10

11

12

VCC

ADIO0

ADIO1

ADIO2

ADIO3

ADIO4

ADIO5

ADIO6

ADIO7

13

14

15

16

17

18

19

20

ADIO8

ADIO9

ADIO10

ADIO11

ADIO12

ADIO13

ADIO14

ADIO15

29

VCC

69

VCC

PF0

PF1

PF2

PF3

PF4

31

32

33

34

35

36

PF5

PF6

PF7

37

38

PG0

PG1

PG2

PG3

PG4

21

22

23

24

25

26

PG5

PG6

27

PG7 28

WR

59

RD

60

BHE 40

ALE

79

80

1

2

RESET 39

71

72

73

74

75

76

77

78

PA0

CNTL0 (WR)

PA1

CNTL1 (RD)

PA2

PA3

CNTL2 (BHE)

PA4

PA5

PD0 (ALE)

PA6

PD1 (CLKIN)

PA7

PD2 (CSI)

PD3 (WRH)

PB0

PB1

PB2

PB3

RESET

PB4

PB5

PB6

PE0 (TMS)

PB7

PE1 (TCK/ST)

PE2 (TDI)

PC0

PE3 (TDO)

PC1

PE4 (TSTAT/RDY)

PC2

PE5 (TERR)

PC3

PE6 (VSTBY)

PC4

PE7 (VBATON)

PC5

PC6

GNDGNDGNDGNDGND PC7

8 30 49 50 70

51

52

53

54

55

56

57

58

61

62

63

64

65

66

67

68

41 A16

42 A17

43 A18

44 A19

45

46

47

48

A[ 19:16]

AD[ 15:0]

AI04930

80C196 and 80C186. In Figure 21, the Intel

80C196 MCU, which has a 16-bit multiplexed ad-

dress/data bus, is shown connected to a

PSD4235G2. The Read Strobe (RD, CNTL1), and

Write Strobe (WR/WRL, CNTL0) signals are con-

nected to the CNTL pins. When BHE is not used,

the PSD can be configured to receive WRL and

Write Enable High-byte (WRH/DBE, PD3) from the

MCU. Higher address inputs (A16-A19) can be

routed to Ports A, B, or C as input ot the PLD.

The AMD 80186 family has the same bus connec-

tion to the PSD as the 80C196.

43/89

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