PSD4214F3V-12UI データシートの表示（PDF） - STMicroelectronics

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PSD4214F3V-12UI

Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

STMicroelectronics 

Figure 23. Interfacing the PSD with an 80C51XA-G3

PSD4235G2

RESET\

U3

CRYSTAL

RESET\

VCC_BAR

XA-G3

21

XTAL1

20

XTAL2

11

13 RXD0

6

7

TXD0

RXD1

TXD1

9

8 T2EX

16 T2

T0

43

A4D0 42

A5D1 41

A6D2 40

A7D3 39

A8D4 38

A9D5 37

A10D6

A11D7

36

A12D8

24

25

A13D9 26

A14D10 27

A15D11 28

A16D12 29

A17D13 30

A18D14 31

A19D15

10

14 RST

15 INT0

INT1

5

A3

A2

A1

A0/WRH

WRL

4

3

2

18

19

RD

32

PSEN

35

EA/WAIT

17

BUSW

33

ALE

A3

A2

A1

WRH\

WRL\

RD\

PSEN\

ALE

VCC_BAR

D[15:0]

A[3:1]

D[15:0]

A[3:1]

PSD

A4D0 3

A5D1 4

A6D2 5

A7D3 6

A8D4 7

A9D5 10

A10D6 11

A11D7 12

A12D8 13

A13D9 14

A14D10 15

A15D11 16

A16D12 17

A17D13 18

A18D14 19

A19D15 20

ADIO0

ADIO1

ADIO2

ADIO3

ADIO4

ADIO5

ADIO6

ADIO7

ADIO8

ADIO9

ADIO10

ADIO11

ADIO12

ADIO13

ADIO14

ADIO15

59

60

CNTL0(WR)

CNTL1(RD)

40

CNTL2(PSEN)

79

80 PD0 (ALE)

1 PD1 (CLKIN)

2 PD2 (CSI)

PD3 (WRH)

39 RESET

71

72 PE0 (TMS)

73 PE1 (TCK/ST)

74 PE2 (TDI)

75 PE3 (TDO)

76 PE4 (TSTAT/RDY)

77 PE5 (TERR)

78 PE6 (VSTBY)

PE7 (VBATON)

31

PF0 32

PF1 33

PF2 34

PF3 35

A1

A2

A3

PF4 36

PF5 37

PF6

PF7

38

PG0

21

22

PG1 23

PG2 24

PG3 25

PG4 26

PG5 27

PG6 28

PG7

51

PA0

PA1

PA2

PA3

PA4

52

53

54

55

56

PA5 57

PA6 58

PA7

61

PB0 62

PB1 63

PB2 64

PB3 65

PB4

PB5

PB6

PB7

66

67

68

41

PC0 42

PC1 43

PC2 44

PC3 45

PC4 46

PC5 47

PC6 48

PC7

80C51XA. The Philips 80C51XA MCU has a 16-

bit multiplexed bus with burst cycles. Address bits

(A3-A1) are not multiplexed, while (A19-A4) are

multiplexed with data bits (D15-D0).

The PSD4235G2 supports the 80C51XA burst

mode. The WRH signal is connected to PD3, and

WHL is connected to CNTL0. The RD and PSEN

signals are connected to the CNTL1 and CNTL2

pins. Figure 23 shows the schematic diagram.

AI04952b

The 80C51XA improves bus throughput and per-

formance by issuing burst cycles to fetch codes

from memory. In burst cycles, address A19-A4 are

latched internally by the PSD, while the 80C51XA

drives the A3-A1 signals to fetch sequentially up to

16 bytes of code. The PSD access time is then

measured from address A3-A1 valid to data in val-

id. The PSD bus timing requirement in a burst cy-

cle is identical to the normal bus cycle, except the

address setup and hold time with respect to Ad-

dress Strobe (ALE/AS, PD0) is not required.

45/89

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