PIC18F46K80T-I/SP データシートの表示（PDF） - Microchip Technology

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PIC18F46K80T-I/SP

28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

Microchip Technology 

PIC18F66K80 FAMILY

18.10 Operation During Sleep/Idle Modes

18.10.1 SLEEP MODE

When the device enters any Sleep mode, the CTMU

module current source is always disabled. If the CTMU

is performing an operation that depends on the current

source when Sleep mode is invoked, the operation may

not terminate correctly. Capacitance and time

measurements may return erroneous values.

18.10.2 IDLE MODE

The behavior of the CTMU in Idle mode is determined

by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL

is cleared, the module will continue to operate in Idle

mode. If CTMUSIDL is set, the module’s current source

is disabled when the device enters Idle mode. In this

case, if the module is performing an operation when

Idle mode is invoked, the results will be similar to those

with Sleep mode.

18.11 Effects of a Reset on CTMU

Upon Reset, all registers of the CTMU are cleared. This

disables the CTMU module, turns off its current source

and returns all configuration options to their default set-

tings. The module needs to be re-initialized following

any Reset.

If the CTMU is in the process of taking a measurement

at the time of Reset, the measurement will be lost. A

partial charge may exist on the circuit that was being

measured, which should be properly discharged before

the CTMU makes subsequent attempts to make a

measurement. The circuit is discharged by setting and

clearing the IDISSEN bit (CTMUCONH<1>) while the

A/D Converter is connected to the appropriate channel.

TABLE 18-1: REGISTERS ASSOCIATED WITH CTMU MODULE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CTMUCONH CTMUEN

—

CTMUSIDL TGEN

EDGEN EDGSEQEN IDISSEN CTTRIG

CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT

CTMUICON ITRIM5 ITRIM4

ITRIM3

ITRIM2

ITRIM1

ITRIM0

IRNG1

IRNG0

PIR3

—

—

RC2IF

TX2IF

CTMUIF CCP2IF CCP1IF

—

PIE3

—

—

RC2IE

TX2IE

CTMUIE

CCP2IE CCP1IE

—

IPR3

—

—

RC2IP

TX2IP

CTMUIP

CCP2IP CCP1IP

—

PADCFG1

RDPU

REPU

RFPU

RGPU

—

—

—

CTMUDS

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.

DS39977F-page 252

 2010-2012 Microchip Technology Inc.

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