STM32F031E6T7(2015) データシートの表示（PDF） - STMicroelectronics

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STM32F031E6T7
(Rev.:2015)

ARM®-based 32-bit MCU with up to 32 Kbyte Flash, 9 timers, ADC and communication interfaces, 2.0 - 3.6 V

STMicroelectronics 

Electrical characteristics

STM32F031x4 STM32F031x6

Table 58. I2C analog filter characteristics(1)

Symbol

Parameter

Min

Max

tAF

Maximum width of spikes that are

suppressed by the analog filter

50(2)

260(3)

1. Guaranteed by design, not tested in production.

2. Spikes with widths below tAF(min) are filtered.

3. Spikes with widths above tAF(max) are not filtered

Unit

ns

SPI/I2S characteristics

Unless otherwise specified, the parameters given in Table 59 for SPI or in Table 60 for I2S

are derived from tests performed under the ambient temperature, fPCLKx frequency and

supply voltage conditions summarized in Table 18: General operating conditions.

Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).

Table 59. SPI characteristics(1)

Symbol

Parameter

Conditions

Min

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master mode

Slave mode

-

-

tr(SCK)

tf(SCK)

tsu(NSS)

th(NSS)

tw(SCKH)

tw(SCKL)

tsu(MI)

tsu(SI)

SPI clock rise and fall

time

NSS setup time

NSS hold time

SCK high and low time

Data input setup time

Capacitive load: C = 15 pF

Slave mode

Slave mode

Master mode, fPCLK = 36 MHz,

presc = 4

Master mode

Slave mode

-

4Tpclk

2Tpclk + 10

Tpclk/2 -2

4

5

th(MI)

Data input hold time

Master mode

4

th(SI)

Slave mode

5

ta(SO)(2) Data output access time Slave mode, fPCLK = 20 MHz

0

tdis(SO)(3) Data output disable time Slave mode

0

tv(SO)

Data output valid time Slave mode (after enable edge)

-

tv(MO)

Data output valid time Master mode (after enable edge)

-

th(SO)

Data output hold time

Slave mode (after enable edge)

11.5

th(MO)

Master mode (after enable edge)

2

DuCy(SCK)

SPI slave input clock

duty cycle

Slave mode

25

18

18

6

-

-

Tpclk/2 + 1

-

-

-

-

3Tpclk

18

22.5

6

-

-

75

MHz

ns

ns

%

1. Data based on characterization results, not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

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