S25FL128SDPNHVB03 データシートの表示（PDF） - Cypress Semiconductor

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S25FL128SDPNHVB03

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

Figure 9.29 Dual Output Read Command Sequence (4-byte Address, 3Ch or 3Bh [ExtAdd=1, LC=11b])

CS#

SCK

IO0

IO1

Phase

7 6 5 4 3 2 1 0 31 30 29 0 6 4 2 0 6 4 2 0

75 31 7 5 31

Instruction

Address

Data 1

Data 2

9.4.4

Quad Output Read (QOR 6Bh or 4QOR 6Ch)

The instruction

6Bh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or

6Bh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or

6Ch is followed by a 4-byte address (A31-A0)

Then the memory contents, at the address given, is shifted out four bits at a time through IO0-IO3. Each nibble (4 bits) is shifted out

at the SCK frequency by the falling edge of the SCK signal.

The maximum operating clock frequency for Quad Output Read command is 104 MHz. For Quad Output Read Mode, there may be

dummy cycles required after the last address bit is shifted into SI before data begins shifting out of IO0-IO3. This latency period (i.e.,

dummy cycles) allows the device’s internal circuitry enough time to set up for the initial address. During the dummy cycles, the data

value on IO0-IO3 is a “don’t care” and may be high impedance. The number of dummy cycles is determined by the frequency of SCK

(refer to Table 7.12, Latency Codes for SDR Enhanced High Performance on page 51).

The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address

in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read

instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back

to 000000h, allowing the read sequence to be continued indefinitely.

The QUAD bit of Configuration Register must be set (CR Bit1=1) to enable the Quad mode capability.

CS#

SCK

IO0

IO1

IO2

IO3

Figure 9.30 Quad Output Read Command Sequence (3-byte Address, 6Bh [ExtAdd=0, LC=01b])

012345678

30 31 32 33 34 35 36 37 38 39 40 41 42 43

Instruction

24 Bit Address

7 6 5 4 3 2 1 0 23

10

8 Dummy Cycles

Data 1

40

Data 2

40

5151

6262

7373

Document Number: 001-98283 Rev. *I

Page 86 of 144

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