PF48F30000ZB0EA データシートの表示（PDF） - Numonyx -> Micron

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PF48F30000ZB0EA

Numonyx® Axcell™ P30-65nm Flash Memory 128-Mbit, 64-Mbit Single Bit per Cell (SBC)

Numonyx -> Micron 

P30-65nm SBC

Figure 11: Example Latency Count Setting Using Code 3

CLK

CE#

ADV#

AA[M[MAAXX:0:1] ]

D[15:0]

0

1

2

Code 3

Address

High-Z

R103

tData

3

4

Data

11.2.3

End of Word Line (EOWL) Considerations

The delay may occur when a burst sequence access crosses a 8-word boundary. That

is, A[3:1] of start address does not equal 0x0. Figure 12, “End of Wordline Timing

Diagram” on page 37 illustrates the end of wordline WAIT state(s), which occur after

the first 8-word boundary is reached. The number of data words and the number of

WAIT states is summarized in Table 15, “End of Wordline Data and WAIT state

Comparison” on page 38 for both P30-130nm and P30-65nm SBC devices.

Figure 12: End of Wordline Timing Diagram

C LK

A [Max :1 ]

D Q[15 :0 ]

A D V#

OE#

W A IT

Latency C ount

D ata

D ata

D ata

EOW L

Datasheet

37

Apr 2010

Order Number:208033-02

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