PIC16LF785-E/SO データシートの表示（PDF） - Microchip Technology

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PIC16LF785-E/SO

20-Pin Flash-Based, 8-Bit CMOS Microcontroller with Two-Phase Asynchronous Feedback PWM Dual High-Speed Comparators and Dual Operational Amplifiers

Microchip Technology 

PIC16F785/HV785

REGISTER 4-2:

U-0

—

bit 7

TRISA: PORTA TRI-STATE REGISTER

U-0

R/W-1

R/W-1

R-1

—

TRISA5(2) TRISA4(2) TRISA3(1)

R/W-1

TRISA2

R/W-1

TRISA1

R/W-1

TRISA0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5-0

bit 0

Unimplemented: Read as ‘0’

TRISA<5:0>: PORTA Tri-State Control bit(1), (2)

1 = PORTA pin configured as an input (tri-stated)

0 = PORTA pin configured as an output

C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: TRISA<3> always reads ‘1’.

2: TRISA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.

4.2 Additional Pin Functions

Every PORTA pin on the PIC16F785/HV785 has an

interrupt-on-change option and a weak pull-up option.

The next three sections describe these functions.

4.2.1 WEAK PULL-UPS

Each of the PORTA pins has an individually configurable

internal weak pull-up. Control bits WPUAx enable or

disable each pull-up. Refer to Register 4-3. Each weak

pull-up is automatically turned off when the port pin is

configured as an output. The pull-ups are disabled on a

Power-on Reset by the RAPU bit in the (OPTION

Register. The weak pull-up on RA3 is automatically

enabled when RA3 is configured as MCLR.

REGISTER 4-3:

U-0

—

bit 7

WPUA: WEAK PULL-UP REGISTER

U-0

R/W-1

R/W-1

R/W-1

—

WPUA5(4) WPUA4(4) WPUA3(3)

R/W-1

WPUA2

R/W-1

WPUA1

R/W-1

WPUA0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

WPUA<5:0>: Weak Pull-up Register bits

1 = Pull-up enabled

0 = Pull-up disabled

Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in Output mode

(TRISA = 0).

3: The RA3 pull-up is automatically enabled when configured as MCLR in the Configuration Word.

4: WPUA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.

DS41249E-page 36

© 2008 Microchip Technology Inc.

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