PSD833F3A-20UI データシートの表示（PDF） - STMicroelectronics

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PSD833F3A-20UI

Flash in-system programmable (ISP) ipherals for 8-bit MCUs, 5 V

STMicroelectronics 

Instructions

PSD8XXFX

Table 11. Status bits(1)(2)(3)

Functional

block

FS0-

FS7/CSBOOT0-

CSBOOT3

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

Flash memory VIH

Data Toggle Error

Polling flag

flag

X

Erase

timeout

X

X

X

1. X = Not guaranteed value, can be read either '1' or ’0.’

2. DQ7-DQ0 represent the data bus bits, D7-D0.

3. FS0-FS7 and CSBOOT0-CSBOOT3 are active high.

7.7

Data Polling flag (DQ7)

t(s) When erasing or programming in Flash memory, the Data Polling flag bit (DQ7) outputs the

complement of the bit being entered for programming/writing on the DQ7 Bit. Once the

c Program instruction or the WRITE operation is completed, the true logic value is read on the

du Data Polling flag bit (DQ7, in a READ operation).

ro ● Data Polling is effective after the fourth WRITE pulse (for a Program instruction) or after

P the sixth WRITE pulse (for an Erase instruction). It must be performed at the address

te being programmed or at an address within the Flash memory sector being erased.

le ● During an Erase cycle, the Data Polling flag bit (DQ7) outputs a ’0.’ After completion of

the cycle, the Data Polling flag bit (DQ7) outputs the last bit programmed (it is a '1' after

so erasing).

b ● If the byte to be programmed is in a protected Flash memory sector, the instruction is

O ignored.

) - ● If all the Flash memory sectors to be erased are protected, the Data Polling flag bit

t(s (DQ7) is reset to '0' for about 100µs, and then returns to the previous addressed byte.

No erasure is performed.

roduc 7.8

Toggle flag (DQ6)

P The PSD offers another way for determining when the Flash memory Program cycle is

tecompleted. During the internal WRITE operation and when either the FS0-FS7 or

leCSBOOT0-CSBOOT3 is true, the Toggle flag bit (DQ6) toggles from '0' to '1' and '1' to '0' on

o subsequent attempts to read any byte of the memory.

bs When the internal cycle is complete, the toggling stops and the data read on the data bus

O D0-D7 is the addressed memory byte. The device is now accessible for a new READ or

WRITE operation. The cycle is finished when two successive READs yield the same output

data.

● The Toggle flag bit (DQ6) is effective after the fourth WRITE pulse (for a Program

instruction) or after the sixth WRITE pulse (for an Erase instruction).

● If the byte to be programmed belongs to a protected Flash memory sector, the

instruction is ignored.

● If all the Flash memory sectors selected for erasure are protected, the Toggle flag bit

(DQ6) toggles to '0' for about 100µs and then returns to the previous addressed byte.

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Doc ID 7833 Rev 7

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