ST72F324J2TCRS データシートの表示（PDF） - STMicroelectronics

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ST72F324J2TCRS

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

On-chip peripherals

ST72324xx-Auto

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

The Data register performs a double function (read and write) since it is composed of two

registers, one for transmission (TDR) and one for reception (RDR).

The TDR register provides the parallel interface between the internal bus and the output

shift register (see Figure 55). The RDR register provides the parallel interface between the

input shift register and the internal bus (see Figure 55).

SCI Baud Rate Register (SCIBRR)

) SCIBRR

t(s 7

6

uc SCP[1:0]

rod R/W

5

4

3

SCT[2:0]

R/W

Reset value: 0000 0000 (00h)

2

1

0

SCR[2:0]

R/W

te P Table 65. SCIBRR register description

le Bit Name

Function

so First SCI Prescaler

Obsolete Product(s) - Ob 7:6 SCP[1:0]

These 2 prescaling bits allow several standard clock division ranges.

00: PR prescaling factor = 1

01: PR prescaling factor = 3

10: PR prescaling factor = 4

11: PR prescaling factor = 13

128/193

Doc ID 13841 Rev 1

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