ST72F324K2TCTRS データシートの表示（PDF） - STMicroelectronics

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ST72F324K2TCTRS

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

On-chip peripherals

Figure 47. Pulse width modulation cycle

ST72324xx-Auto

When

counter

= OC1R

OCMP1 = OLVL1

When

counter

= OC2R

OCMP1 = OLVL2

counter is reset

to FFFCh

ICF1 bit is set

) If OLVL1 = 1 and OLVL2 = 0, the length of the positive pulse is the difference between the

t(s OC2R and OC1R registers.

c If OLVL1 = OLVL2, a continuous signal will be seen on the OCMP1 pin.

du The OC1R register value required for a specific timing application can be calculated using

ro the following formula:

te P OCiR value = t * fCPU - 5

PRESC

ole Where:

bs t

= Signal or pulse period (in seconds)

O fCPU = CPU clock frequnency (in hertz)

- PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Table 50)

t(s) If the timer clock is an external clock the formula is:

uc OCiR = t * fEXT - 5

rod Where:

P t

= Signal or pulse period (in seconds)

tefEXT = External timer clock frequency (in hertz)

leThe Output Compare 2 event causes the counter to be initialized to FFFCh (see Figure 46).

so Note: 1 After a write instruction to the OCiHR register, the output compare function is inhibited until

Ob the OCiLR register is also written.

2 The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output

Compare interrupt is inhibited.

3 The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce

a timer interrupt if the ICIE bit is set and the I bit is cleared.

4 In PWM mode the ICAP1 pin cannot be used to perform input capture because it is not

connected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be

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Doc ID 13841 Rev 1

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