QL82SD-5PS484C データシートの表示（PDF） - QuickLogic Corporation

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QL82SD-5PS484C

LVDS SERDES, flexible programmable logic, dual port SRAM.

QuickLogic Corporation 

QL82SD Device Data Sheet Rev C

IEEE Standard 1149.1a

The QuickSD device supports IEEE standard 1149.1a. The following public instructions are

supported: BYPASS, EXTEST, and SAMPLE/PRELOAD. Two additional modes RAMWT

and RAMRD can be used to load the RAM.

TCK

TMS

TRSTB

Tap Controller

State Machine

(16 States)

Instruction Decode

&

Control Logic

RDI

Mux

Instruction Register

Boundary-Scan Register

(Data Register)

Bypass

Register

Mux TDO

Logic Cell

Array

I/O Registers

User Defined Data Register

Figure 55: JTAG Block Diagram

JTAG BSDL Support

• BSDL-Boundary Scan Description Language

• Machine-readable data for test equipment to generate testing vectors and software

• BSDL files available for all device/ package combinations from QuickLogic

• Extensive industry support available and ATG (Automatic Test-vector Generation)

Security Fuses

There are two security links, one to disable reading from the array and the other to disable

JTAG.

8-bit Programming

The QuickSD device has 8-bit programming capability. The addition of four extra

programming supplies is used in the reduction of programming time.

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www.quicklogic.com

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Preliminary

© 2002 QuickLogic Corporation

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