ST72325S6B5(2007) データシートの表示（PDF） - STMicroelectronics

部品番号

コンポーネント説明

メーカー

ST72325S6B5
(Rev.:2007)

8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 5 timers, SPI, SCI, I2C interface

STMicroelectronics 

10-BIT A/D CONVERTER (ADC) (Cont’d)

10.8.6 Register Description

CONTROL/STATUS REGISTER (ADCCSR)

Read/Write (Except bit 7 read only)

Reset Value: 0000 0000 (00h)

7

0

EOC SPEED ADON 0 CH3 CH2 CH1 CH0

Bit 7 = EOC End of Conversion

This bit is set by hardware. It is cleared by hard-

ware when software reads the ADCDRH register

or writes to any bit of the ADCCSR register.

0: Conversion is not complete

1: Conversion complete

Bit 6 = SPEED ADC clock selection

This bit is set and cleared by software.

0: fADC = fCPU/4

1: fADC = fCPU/2

Bit 5 = ADON A/D Converter on

This bit is set and cleared by software.

0: Disable ADC and stop conversion

1: Enable ADC and start conversion

Bit 4 = Reserved. Must be kept cleared.

Bit 3:0 = CH[3:0] Channel Selection

These bits are set and cleared by software. They

select the analog input to convert.

Channel Pin*

CH3 CH2 CH1 CH0

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

*The number of channels is device dependent. Refer to

the device pinout description.

DATA REGISTER (ADCDRH)

Read Only

Reset Value: 0000 0000 (00h)

7

0

D9 D8 D7 D6 D5 D4 D3 D2

Bit 7:0 = D[9:2] MSB of Converted Analog Value

DATA REGISTER (ADCDRL)

Read Only

Reset Value: 0000 0000 (00h)

7

0

0

0

0

0

0

0

D1 D0

Bit 7:2 = Reserved. Forced by hardware to 0.

Bit 1:0 = D[1:0] LSB of Converted Analog Value

134/196

Share Link: