AD362SD データシートの表示（PDF） - Analog Devices

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AD362SD

Precision Sample-and-Hold with 16-Channel Multiplexer

Analog Devices 

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When the channel address is changed, six microseconds must

Analo!! Inout Section Offset Adjust Circuit

be allowed for the Analog Input Section to settle to within

Although the offset voltage of the AD362 may be adjusted,

:to.Ol % of its final output (including settling times of all

elements in the signal path). The effect of this delay may be

. eliminated by performing the address change while a conver-

sion is in progress (with the sample-and-hold in the "Hold"

mode).

that adjustment is normally performed at the ADC. In some

special applications, however, it may be helpful to adjust the

offset of the Analog Input Section. An example of such a case

would be if the input signals were small «10mV) relative to

AD362 voltage offset and gain was to be inserted between the

8.

Inout Channel Address Latch

The AD362 is equipped with a latch for the Input Channel

AD362 and the ADC. To adjust the offset of the AD362, the

circuit shown in Figure 5 is recommended.

Select address bits. If the Latch Control pin (pin 32) is at

Logic "1 ", input channel select address information is passed

through to the multiplexers. A Logic "0" "freezes" the input

AD362

ANALOG

INPUT

SECTION

channeraddress present at the inputs at the "1"-to-"O" tran-

sition (level-triggered).

16

OUTPUT

This feature is useful when input channel address information

is provided from an address, data or control bus that may be

required to serv:ce many devices. The ability to latch an

OBSOLETE88 address is helpful whenever the user has no control of when

address information may change.

Samole-and-Hold Mode Control

The Sample-and-Hold Mode Control input (pin 13) is normally

connected to the Status output (pin 20) from an analog to

digital converter. When a conversion is initiated by applying a

Convert Start command to the ADC, Status goes to Logic" 1",

putting the sample-and-hold into the "Hold" mode. This

"freezes" the information to be digitized for the period of

conversion. When the conversion is complete, Status returns

to Logic "0" and the sample-and-hold returns to the "Sample"

mode. Eighteen microseconds must be allowed for the sample-

and-hold to acquire ("catch up" to) the analog input to within

:to.Ol % of the final value before a new Convert Start com-

mand is issued.

The purpose of a sample-and-hold is to "stop" fast changing

input signals long enough to be converted. In this application,

it also allows the user to change channels and/or SEt DIFF

Figure 5. AD362 Offset Voltage Adjustment

Under normal conditions, all calibration is performed at the

ADC Section.

Other Considerations

Grounding: Analog and digital signal grounds should be kept

separate where possible to prevent digital signals from flowing

in the analog ground circuit and inducing spurious analog sig-

nal noise. Analog Ground (pin 17) and Digital Ground (pin 2)

are not connected internally; these pins must be connected

externally for the system to operate properly. Preferably, this

connection is made at only one point, as close to the AD362

as possible. The case is connected internally to Digital Ground

to provide good electrostatic shielding. If the grounds are not

mode while a conversion is in progress thus eliminating the

tied common on the same card with the AD362, the digital

effects of multiplexer, analog switch and differential amplifier and analog grounds should be connected locally with back-to-

settling times. If maximum throughput rate is required for

back general-purpose diodes as shown in Figure 6. This will

slowly changing signals, the Sample-and-Hold Mode Control

protect the AD362 from possible damage caused by voltages

may be wired to ground (Logic "0") rather than to ADC

in excess of :tl volt between the ground systems which could

,tatus thus leaving the sample-and-hold in a continuous

occur if the key grounding card should be removed from the

;ample mode.

overall system. The device will operate properly with as much

as :t200m V between grounds, however this difference will be

lold Caoacitor

reflected directly as an input offset voltage.

\ 2000pF capacitor is provided with each AD362. One side

)f this capacitor is wired to pin 12, the other to analog ground

as close to pin 17 as possible. The capacitor provided with the

AD362KD is Polystyrene while the wider operating temperature

AD362

ADC

range of the AD362SD requires a Teflon capacitor (supplied).

DGND

AGND

Smaller capacitors will allow slightly faster operation, but only

with increased noise and decreased precision. 1000pF will

typically allow acquisition to 0.1 % in four microseconds.

TO

CARD

CONNECTOR

Larger capacitors may be substituted to reduce noise, and

sample-to-hold offset, but acquisition time of the sample-and-

Figure 6. Ground-Fault Protection Diodes

hold will be extended. If less than 12 bits of accuracy is re-

quired, a smaller capacitor may be used. This will shorten the

Power Supply Bypassing: The :t15V and +5V power leads

S/H acquisition time. In all cases, the proper capacitor die-

should be capacitively bypassed to Analog Ground and Digital

lectric must be used; i.e., Polystyrene (AD326KD only) or

Ground respectivelyfor optimum device performance. IJ.LF

Teflon (AD362KD or SD). Other types of capacitors may

have higher dielectric absorption (memory) and will cause

tantalum types are recommended; these capacitors should be

located close to the system. It is not necessary to shunt these

,

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errors. CAUTION: Polystyrene capacitors will be destroyed

capacitors with disc capacitors to provide additional high

if subjected to temperatures above +850 C. No capacitor is

frequency power supply decoupling since each power lead is

required if the sample-and-hold is not used.

bypassed internally with a 0.039J.LFceramic capacitor.

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