ZPSD403A2-C-70L 데이터 시트보기 (PDF) - STMicroelectronics

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ZPSD403A2-C-70L

Low Cost Field Programmable Microcontroller Peripherals

STMicroelectronics 

PSD4XX Family

The PSD4XX

Architecture

(cont.)

9.1.2 The PSD4XXA2 ZPLD Block

Key Features

t 2 Embedded ZPLD devices

t 24 macrocells

t Combinatorial/registered outputs

t Maximum 126 product terms

t Programmable output polarity

t User configured register clear/preset

t User configured register clock input

t 59 Inputs

t Accessible via 24 I/O pins

t Power Saving Mode

t UV-Erasable

General Description

The ZPLD block has 2 embedded PLD devices:

t DPLD

The Address Decoding PLD, generating select signals to internal I/O or memory blocks.

t GPLD

The General Purpose PLD provides 24 programmable macrocells for general

or complex logic implementation; dedicated to user application.

Figure 11 shows the architecture of the ZPLD. The PLD devices all share the same

input bus. The true or complement of the 59 input signals are fed to the programmable

AND-ARRAY. Names and source of the input signals are shown in Table 4. The PA, PB, PE

signals, depending on user configuration, can either be macrocell feedbacks or inputs from

Port A, B or E.

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