PSD412A2-C-90UI 데이터 시트보기 (PDF) - STMicroelectronics
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PSD412A2-C-90UI Datasheet PDF : 123 Pages
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PSD4XX Family
10.0
Page
Register
The Page Register is 4 bits wide and consists of four D flip flops.The outputs of the Register
(PGR0 – PGR3) are connected to the input bus of the ZPLD. By including the four outputs
as inputs to the DPLD, the addressing capability of the microcontroller is increased by a
factor of 16.
Figure 37 shows the Page Register block diagram. Inputs to the four flip flops are connected
to data bus D0-D3. The output of the Register can be read by the microcontroller. The
Register can operate as an independent register to the microcontroller if page mode is not
implemented.
Figure 35. Page Register
RESET
D0 – D3
R/W
PGR0
D0
Q0
PGR1
D1
Q1
PGR2
D2
Q2
PGR3
D3
Q3
PAGE
REG.
DPLD
ES0 – 3
RS0
GPLD
ZPLD
11.0
Security
Protection
The PSD4XX has a programmable security bit which offers protection from unauthorized
duplication. When the security bit is set, the contents of the EPROM, the PSD4XX
non-volatile configuration bits and ZPLD data cannot be read by EPROM programmers.
The security bit is set through the PSDsoft Software and is embedded in the compiled
output file. The security bit is UV erasable and a secured part can be erased and then
re-programmed.
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