UT1750AR12WCCR 데이터 시트보기 (PDF) - Aeroflex UTMC

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UT1750AR12WCCR

RISC Microprocessor

Aeroflex UTMC 

Table 5. RISC Macro Locations for

Valid 1750 Opcodes Between 00H and 4FH

1750

INSTRUCTION

LB

DLB

STB

DSTB

AB

SBB

MB

DB

FAB

FSB

FMB

FDB

ORB

ANDB

CB

FCB

LBX

DLBX

STBX

DSTX

ABX

SBBX

MBX

DBX

FABX

FSBX

FMBX

FDBX

CBX

FCBX

ANDX

ORBX

XIO

VIO

AIM

SIM

MIM

MSIM

DIM

DVIM

ANDM

ORIM

XORM

CIM

NIM

BIF

1750

OPCODE(S)

00 TO 03

04 TO 07

08 TO 0B

0C TO 0F

10 TO 13

14 TO 17

18 TO 1B

1C TO 1F

20 TO 23

24 TO 27

28 TO 2B

2C TO 2F

30 TO 33

34 TO 37

38 TO 3B

3C TO 3F

400 TO 430

401 TO 431

402 TO 432

403 TO 433

404 TO 434

405 TO 435

406 TO 436

407 TO 437

408 TO 438

409 TO 439

40A TO 43A

40B TO 43B

40C TO 43C

40D TO 43D

40E TO 43E

40F TO 43F

48

49

4AX1

4AX2

4AX3

4AX4

4AX5

4AX6

4AX7

4AX8

4AX9

4AXA

4AXB

4F

RISC MACRO

LOCATION

0020

0060

00A0

00E0

0120

0160

01A0

01E0

0220

0260

02A0

02E0

0320

0360

03A0

03E0

0030

0070

00B0

00F0

0130

0170

01B0

01F0

0230

0270

02B0

02F0

0330

0370

03B0

03F0

0480

0490

0050

0090

00D0

0110

0150

0190

01D0

0210

0250

0290

02D0

04F0

PROGRAMMING INTERFACE

Data Formats

The UT1750AR instruction set supports 16-bit integer single-

precision data and 32-bit integer double- precision data. When

the UT1750AR is operating in the 1750 mode with the 1750

emulation code in the RISC PROMs, the UT1750AR can

emulate 32-bit floating-point and 8-bit floating-point extended-

precision data. All data is in 2’s complement representation.

MSB

LSB

SIGN

DATA

15 14

0

Figure 31a. Single 6Precision Fixed-Point Data

MSB

LSB

SIGN

(MSH)

(LSH)

31 30

16 15

0

Figure 31b. Double 06Precision Fixed-Point Data

The UT1750AR represents the fixed-point data formats as a 2’s

complement integer with the MSB as the sign bit (figures 31a

and 31b).

Operand Size

The UT1750AR’s instruction set supports three operand sizes:

(1) Byte (eight bits); (2) Word (16 bits); and (3) Long Word (32

bit). Byte operands are only allowed with byte instructions. All

other instructions support word and long-word operands.

Organization of Data in General Purpose Registers

All 20 of the UT1750AR’s general purpose data registers

support bit, byte, and word operations. When the system

programmer specifies a byte operation in a specific instruction,

the instruction expects to find the byte of Operand Data in the

least significant eight bits of the data register. The least

significant bit of each of the data registers is bit 0 and the most

significant bit of each of the data registers is bit 15. Any one of

the data registers may be the source or destination for the

operand.

For long-word operands, the UT1750AR organizes the 20

general purpose data registers as 10 even/odd register pairs. The

even-numbered register of the register pair contains the most

significant word. All register pairs may be the source or

destination operands.

34

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