PIC18F010T-I/SN 데이터 시트보기 (PDF) - Microchip Technology

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PIC18F010T-I/SN

High Performance Microcontrollers

Microchip Technology 

PIC18F010/020

TABLE 13-2: PIC18F010/020 INSTRUCTION SET (CONTINUED)

Mnemonic,

Operands

Description

16-Bit Instruction Word

Cycles

MSb

LSb

Status

Affected

Notes

CONTROL OPERATIONS

BC

n

BN

n

BNC

n

BNN

n

BNOV n

BNZ

n

BOV

n

BRA

n

BZ

n

CALL

n, s

CLRWDT —

DAW

—

GOTO n

NOP

—

NOP

—

POP

—

PUSH —

RCALL n

RESET

RETFIE s

RETLW k

RETURN s

SLEEP —

Branch if Carry

Branch if Negative

Branch if Not Carry

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

Branch if Overflow

Branch Unconditionally

Branch if Zero

Call subroutine1st word

2nd word

Clear Watchdog Timer

Decimal Adjust WREG

Go to address1st word

2nd word

No Operation

No Operation (Note 4)

Pop top of return stack (TOS)

Push top of return stack (TOS)

Relative Call

Software device RESET

Return from interrupt enable

1 (2)

1 (2)

1 (2)

1 (2)

1 (2)

2

1 (2)

1 (2)

1 (2)

2

1

1

2

1

1

1

1

2

1

2

Return with literal in WREG

2

Return from Subroutine

2

Go into Standby mode

1

1110

1110

1110

1110

1110

1110

1110

1101

1110

1110

1111

0000

0000

1110

1111

0000

1111

0000

0000

1101

0000

0000

0010

0110

0011

0111

0101

0001

0100

0nnn

0000

110s

kkkk

0000

0000

1111

kkkk

0000

xxxx

0000

0000

1nnn

0000

0000

nnnn

nnnn

nnnn

nnnn

nnnn

nnnn

nnnn

nnnn

nnnn

kkkk

kkkk

0000

0000

kkkk

kkkk

0000

xxxx

0000

0000

nnnn

1111

0001

0000 1100 kkkk

0000 0000 0001

0000 0000 0000

nnnn

nnnn

nnnn

nnnn

nnnn

nnnn

nnnn

nnnn

nnnn

kkkk

kkkk

0100

0111

kkkk

kkkk

0000

xxxx

0110

0101

nnnn

1111

000s

kkkk

001s

0011

None

None

None

None

None

None

None

None

None

None

TO, PD

C

None

None

None

None

None

None

All

GIE/GIEH,

PEIE/GIEL

None

None

TO, PD

Note 1:

2:

3:

4:

5:

6:

When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an

external device, the data will be written back with a '0'.

If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if

assigned.

If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP, unless the

first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory

locations have a valid instruction.

If the table write starts the write cycle to internal memory, the write will continue until terminated.

Microchip Assembler MASM automatically defaults destination bit ’d’ to ’1’, while access bit ’a’ defaults to ’1’ or ’0’

according to address of register being used.

 2001 Microchip Technology Inc.

Preliminary

DS41142A-page 99

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