ST62E08BT3/SWD 데이터 시트보기 (PDF) - STMicroelectronics

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ST62E08BT3/SWD

8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET

STMicroelectronics 

ST6208C/ST6209C/ST6210C/ST6220C

6 INTERRUPTS

The ST6 core may be interrupted by four maska-

ble interrupt sources, in addition to a Non Maska-

ble Interrupt (NMI) source. The interrupt process-

ing flowchart is shown in Figure 18.

Maskable interrupts must be enabled by setting

the GEN bit in the IOR register. However, even if

they are disabled (GEN bit = 0), interrupt events

are latched and may be processed as soon as the

GEN bit is set.

Each source is associated with a specific Interrupt

Vector, located in Program space (see Table 8). In

the vector location, the user must write a Jump in-

Figure 17. Interrupts Block Diagram

VDD

struction to the associated interrupt service rou-

tine.

When an interrupt source generates an interrupt

request, the PC register is loaded with the address

of the interrupt vector, which then causes a Jump

to the relevant interrupt service routine, thus serv-

icing the interrupt.

Interrupt are triggered by events either on external

pins, or from the on-chip peripherals. Several

events can be ORed on the same interrupt vector.

On-chip peripherals have flag registers to deter-

mine which event triggered the interrupt.

NMI

LATCH

PA0...P A3

I/O PORT REGISTER

“INPUT WITH INTERRUPT”

CONFIGURATION

CLEARED BY H/W

AT START OF VECTOR #0 ROUTINE

LATCH

0

CLEARED BY H/W

AT START OF

VECTOR #1 ROUTINE

1

LES BIT

(IOR REGISTER)

VECTOR #0

VECTOR #1

EXIT FROM

STOP/WAI T

PB 0...PB7

I/O PORT REGISTER

“INPUT WITH INTERRUPT”

CONFIGURATION

LATCH

ESB BIT

(IOR REGISTER) CLEARED

BY H/W AT START OF

VECTOR #2 ROUTINE

TMZ BIT

TIMER ETI BIT

(TSCR REGISTER)

A/D

CONVE RTER

*

EAI

EOC

BIT

BI T

(ADCR REGISTER)

GEN BIT

(IOR REGISTE R)

* Depending on device. See device summary on page 1.

VECTO R #2

VECTOR #3

VECTOR #4

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