Z8018533FSC 데이터 시트보기 (PDF) - Zilog

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Z8018533FSC

SMART PERIPHERAL CONTROLLERS

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PRELIMINARY

EMSCC REGISTERS (Continued)

Z80185/Z80195

SMART PERIPHERAL CONTROLLES

WR' Prime

D7 D6 D5 D4 D3 D2 D1 D0

Auto Tx Flag

Auto EOM Reset

Auto RTS Deactivation

Rx FIFO Int Level

Tx DMA Request Timing Mode

Tx FIFO Int Level

Extended Read Enable

32-Bit CRC Enable

Write Register 10

D7 D6 D5 D4 D3 D2 D1 D0

0 0 NRZ

0 1 NRZI

1 0 FM1 (Transition = 1)

1 1 FM0 (Transition = 0)

6-Bit//8-Bit Sync

Loop Mode

Abort//Flag On Underrun

Mark//Flag Idle

Go Active On Poll

CRC Preset I//O

Write Register 9

D7 D6 D5 D4 D3 D2 D1 D0

0 0 No Reset

0 1 Not used

1 0 Channel Reset

1 1 Force Hardware Reset

VIS

NV

DLC

MIE

Status High//Status Low

Software INTACK Enable

Write Register 11

D7 D6 D5 D4 D3 D2 D1 D0

0 0 /TRxC Out = Xtal Output

0 1 /TRxC Out = Transmit Clock

1 0 /TRxC Out = BR Generator Output

1 1 /TRxC Out = DPLL Output

/TRxC O/I

0 0 Transmit Clock = /RTxC Pin

0 1 Transmit Clock = /TRxC Pin

1 0 Transmit Clock = BR Generator Output

1 1 Transmit Clock = DPLL Output

0 0 Receive Clock = /RTxC Pin

0 1 Receive Clock = /TRxC Pin

1 0 Receive Clock = BR Generator Output

1 1 Receive Clock = DPLL Output

Reserved

Figure 70. Write Register Bit Functions (Continued)

DS971850301

61

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