STPCI2(2002) 데이터 시트보기 (PDF) - STMicroelectronics
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STPCI2 Datasheet PDF : 111 Pages
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ELECTRICAL SPECIFICATIONS
4.5.1. POWER ON SEQUENCE
Figure 4-3 describes the power-on sequence of
the STPC, also called cold reset.
Strap Options are continuously sampled during
SYSRSTI# low and must remain stable. Once
SYSRSTI# is high, they MUST NOT CHANGE
until SYSRSTO# goes high.
There is no dependency between the different
power supplies and there is no constraint on their
rising time.
SYSRSTI# as no constraint on its rising edge but
must stay active until power supplies are all within
specifications, a margin of 10µs is even
recommended to let the STPC PLLs and strap
options stabilize.
Bus activity starts only few clock cycles after the
release of SYSRSTO#. The toggling signals
depend on the STPC configuration.
In ISA mode, activity is visible on PCI prior to the
ISA bus as the controller is part of the south
bridge.
In Local Bus mode, the PCI bus is not accessed
and the Flash Chip Select is the control signal to
monitor.
Figure 4-3. Power-on timing diagram
Power Supplies
14 MHz
SYSRSTI#
> 10 us
1.6 V
ISACLK
Strap Options
HCLK
PCI_CLK
SYSRSTO#
48/111
VALID CONFIGURATION
2.3 ms
Issue 1.0 - July 24, 2002
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