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STPCI2GDYI

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

2 PIN DESCRIPTION

2.1. INTRODUCTION

example, when in the ISA mode, the Local Bus is

disabled totally and Local Bus pins are set to the

The STPC Atlas integrates most of the

functionalities of the PC architecture. Therefore,

many of the traditional interconnections between

tri-state (high-impedance) condition.

Table 2-1. Signal Description

the host PC microprocessor and the peripheral

devices are totally internal to the STPC Atlas. This

offers improved performance due to the tight

coupling of the processor core and it’s peripherals.

As a result many of the external pin connections

are made directly to the on-chip peripheral

functions.

Group name

Basic Clocks, Reset & Xtal (SYS)

SDRAM Controller (SDRAM)

PCI Controller

ISA Controller

Local Bus I/F

PCMCIA Controller

Qty

19

95

51

80

67

62

100

Table 2-1 describes the physical implementation IDE Controller

34

listing signal types and their functionalities. Table VGA Controller (VGA) / I2C

10

2-2 provides a full pin listing and description.

) Table 2-6 provides a full listing of the STPC Atlas

t(s package pin location physical connection. Please

refer to the pin allocation drawing for reference.

uc Due to the number of pins available for the

d package, and the number of functional I/Os, some

ro pins have several functions, selectable by strap

option on Reset. Table 2-4 provides a summary of

P these pins and their functions.

te Non multi-functional pins associated with a

le particular function are not available for use

o elsewhere when that function is disabled. For

Video Input Port

TFT output

USB Controller

Serial Interface

Keyboard/Mouse Controller

Parallel Port

GPIO Signals

JTAG Signals

Miscellaneous

Grounds

VDD 3.3 V/2.5 V

Reserved

Total Pin Count

Obs Table 2-2. Definition of Signal Pins

) - Signal Name

Dir

Buffer Type1

t(s BASIC CLOCKS AND RESETS

c SYSRSTI#

I SCHMITT_FT

u SYSRSTO#

O BD8STRP_FT

d XTALI

ro XTALO

P PCI_CLKI

te PCI_CLKO

le ISA_CLK,

o ISA_CLK2X

s OSC14M

bHCLK

ODEV_CLK

I OSCI13B

O

I TLCHT_FT

O BT8TRP_TC

O BT8TRP_TC

O BD8STRP_FT

I/O BD4STRP_FT

O BT8TRP_TC

Description

System Reset / Power good

Reset Output to System

14.31818 MHz Crystal Input

External Oscillator Input

14.31818 MHz Crystal Output

33 MHz PCI Input Clock

33 MHz PCI Output Clock

ISA Clock x1 and x2

Multiplexer Select Line for IPC

ISA bus synchronisation clock

66 MHz Host Clock (Test pin)

24 MHz Peripheral Clock

11

24

6

16

4

18

16

5

5

96

36

4

516

Qty

1

1

1

1

1

1

2

1

1

1

DCLK

I/O BD4STRP_FT

135 MHz Dot Clock

1

VDD_xxx_PLL

2.5V Power Supply for PLL Clocks

7

MEMORY CONTROLLER

MCLKI

I TLCHT_TC

Memory Clock Input

1

MCLKO

O BT8TRP_TC

Memory Clock Output

1

Note1; See Table 2-3 for buffer type descriptions

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1

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