CL-PS7500FE 데이터 시트보기 (PDF) - Cirrus Logic

부품명

상세내역

제조사

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

18.5 The Floating-Point Control Register (FPCR)

The Floating-Point Control register (FPCR) is an implementation-specific register: it may not exist in some

versions of the ARM floating-point system and, when it does exist, it may contain different information for

different versions of the system.

When present, it is used for internal communication within the floating point system and, in particular, to

allow software and hardware components of the system to communicate with each other.

Use of the WFC and RFC instructions outside the floating-point system itself is strongly discouraged. In

the case of User mode programs, it is actually prohibited: the WFC and RFC instructions will trap if exe-

cuted in User mode.

The FPCR within the CL-PS7500FE has an FPCR. It enables and disables the device and communicates

information about instructions the hardware cannot handle to the support code.

The FPA FPCR bit allocation is as follows:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RU R R IE MO EO R R

OP

PR

S1

OP DS SB AB RE DA PR RM OP

S2

31

RU

30

29

28

IE

27

MO

26

EO

25

24

23:20 OP

19, 7 PR

18:16 S1

15

OP

14:12 DS

11

SB

10

AB

9

RE

8

DA

6:5

RM

4

OP

3:0

S2

Rounded-up bit

Reserved

Reserved

Inexact bit

Mantissa overflow

Exponent overflow

Reserved

Reserved

AU operation code

AU precision

AU source register 1

AU operation code

AU destination register

Store bounce: decode (R14) to get opcode

Arithmetic bounce: opcode supplied in rest of word

Rounding Exception: Arithmetic bounce occurred during rounding stage

and destination register was written

Disable FPA

AU rounding mode

AU operation code

AU source register 2 (bit 3 set denotes a constant)

168

FLOATING-POINT COPROCESSOR PROGRAMMER’S

MODEL

ADVANCE DATA BOOK v2.0

June 1997

Share Link: