CL-PS7500FE 데이터 시트보기 (PDF) - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

comparators in the A-to-D converters do not consume current, they should be shut down by programming

the value 0x00 to the ATODICR register at location 0x032000E0.

CL-PS7500FE includes support for self refresh DRAM, and it is intended that this feature should be used

during STOP mode to ensure that DRAM contents are preserved. This DRAM mode is activated by allow-

ing direct software control of the nCAS and nRAS output pins. The SELFREF register (0x032000D4) can

be used to directly force the nRAS and nCAS output pins according to the protocol required for a particular

DRAM to enter self-refresh mode. This programming must be performed by code executing from ROM.

In STOP mode CL-PS7500FE consumes leakage currents only, and can be held indefinitely without cor-

ruption of the internal registers, CPU cache, etc.

21.3 Reset

The CL-PS7500FE has three pins associated with reset. The nPOR pin is intended for use with an exter-

nal RC delay to generate a power-on-reset pulse when the chip is switched on. The nRESET pin is an

open drain I/O pin, intended to generate a ‘soft’ reset. Both nPOR and nRESET are active low schmitt

inputs. The active high RESET pin is a clean reset output, created from the synchronized version of the

nRESET input, and is also forced high during nPOR.

A low state on the nPOR input sets the POR bit in the IRQA status register. This bit can later be examined

to show that the reset that occurred was an nPOR type rather than nRESET. The POR bit in the IRQA

status register is not reset until the POR clear bit in the IRQA request register is written to. nPOR also

causes the prescalars on the clock inputs to be set to divide by 2. The nPOR input is passed through a

pulse stretcher that ensures that even a short pulse on the input guarantees a full reset of the whole of

CL-PS7500FE. During nPOR reset, nCAS is forced low throughout and the nRAS outputs are changed.

While nPOR is low, nRESET and ID (both open drain pins) are held low, and an incrementing address

value is output on the LA address bus.

A low state on the nRESET input is used to generate a ‘soft’ reset. This does not set any interrupt flags,

and the nRESET low state must exist for longer than 1us to guarantee that it is seen, as it is passed

through a synchronizer before being used by the internal circuitry. At the start of the nRESET active

period, the whole CL-PS7500FE (including the DRAM refresh state machine and counter) is reset for

1-µs, and for the remaining duration of the nRESET pulse, DRAM refresh takes place at the highest

selectable rate. During nRESET, the ARM processor outputs an incrementing address on the LA bus.

June 1997

ADVANCE DATA BOOK v2.0

CLOCKS, POWER SAVING, AND RESET

195

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