CL-PS7500FE 데이터 시트보기 (PDF) - Cirrus Logic
부품명
상세내역
제조사
CL-PS7500FE Datasheet PDF : 251 Pages
| |||
CL-PS7500FE
System-on-a-Chip for Internet Appliance
There are three routes for address translation and permission checking. The selected route depends on
if the address in question is marked as a section-mapped access or a page-mapped access; there are
two sizes of page-mapped access (large pages and small pages). However, the translation process
always starts out in the same way, as described in Section 6.3.2, with a Level One fetch. A section-
mapped access only requires a Level One fetch, but a page-mapped access also requires a Level Two
fetch.
6.3 Translation Process
6.3.1 TTB (Translation Table Base)
The translation process is initiated when the on-chip TLB does not contain an entry for the requested vir-
tual address. The TTB register points to the base of a table in physical memory that contains Section
and/or Page descriptors. The 14 low-order bits of the TTB register are set to zero as illustrated in
Figure 6-2, the table must reside on a 16-Kbyte boundary.
31
14 13
0
TRANSLATION TABLE BASE
Figure 6-2. Translation Table Base Register
6.3.2 Level One Fetch
Bits 31:14 of the TTB register are concatenated with bits 31:20 of the virtual address to produce a 30-bit
address, as illustrated in Figure 6-3. This address selects a 4-byte translation table entry that is a First
Level descriptor for either a Section or a Page (bit 1 of the descriptor returned specifies if it is for a Section
or Page).
VIRTUAL ADDRESS
31
20 19
0
TABLE INDEX
SECTION INDEX
TRANSLATION TABLE BASE
31
14 13
0
TRANSLATION BASE
18
31
TRANSLATION BASE
14 13
12
TABLE INDEX
21 0
00
31
FIRST LEVEL DESCRIPTOR
0
Figure 6-3. Accessing the Translation Table First Level Descriptors
40
ARM PROCESSOR MMU
ADVANCE DATA BOOK v2.0
June 1997
Share Link: 