PIC16C505
10.3 DC CHARACTERISTICS:
PIC16C505-04 (Commercial, Industrial, Extended)
PIC16C505-20(Commercial, Industrial, Extended)
PIC16LC505-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions (unless otherwise specified)
Operating temperature 0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating voltage VDD range as described in DC spec Section 10.1 and
Section 10.3.
Sym Min Typ† Max Units
Conditions
Input Low Voltage
I/O ports
VIL
D030
with TTL buffer
VSS — 0.8V V For all 4.5 ≤ VDD ≤ 5.5V
D030A
VSS — 0.15VDD V otherwise
D031
with Schmitt Trigger buffer
VSS
— 0.2VDD V
D032 MCLR, RC5/T0CKI
VSS
— 0.2VDD V
(in EXTRC mode)
D033 OSC1 (in XT, HS and LP)
VSS — 0.3VDD V Note1
Input High Voltage
I/O ports
VIH
—
D040
with TTL buffer
2.0
— VDD V 4.5 ≤ VDD ≤ 5.5V
D040A
0.25VDD — VDD
+ 0.8VDD
V
otherwise
D041
with Schmitt Trigger buffer
0.8VDD — VDD V For entire VDD range
D042 MCLR, RC5/T0CKI
0.8VDD — VDD V
D042A OSC1 (XT, HS and LP)
0.7VDD — VDD V Note1
D043 OSC1 (in EXTRC mode)
0.9VDD — VDD V
D070 GPIO weak pull-up current (Note 4) IPUR
50 250 400 µA VDD = 5V, VPIN = VSS
Input Leakage Current (Notes 2, 3)
D060 I/O ports
IIL
—
— ±1 µA Vss ≤ VPIN ≤ VDD, Pin at
hi-impedance
D061 GP3/MCLRI (Note 5)
—
— ±30 µA Vss ≤ VPIN ≤ VDD
D061A GP3/MCLRI (Note 6)
—
—
±5
µA Vss ≤ VPIN ≤ VDD
D063 OSC1
—
— ±5 µA Vss ≤ VPIN ≤ VDD, XT, HS and LP
osc configuration
Output Low Voltage
D080 I/O ports/CLKOUT
VOL
—
— 0.6
V IOL = 8.5 mA, VDD = 4.5V,
–40°C to +85°C
D080A
—
— 0.6
V IOL = 7.0 mA, VDD = 4.5V,
–40°C to +125°C
D083 OSC2
—
— 0.6
V IOL = 1.6 mA, VDD = 4.5V,
–40°C to +85°C
D083A
—
— 0.6
V IOL = 1.2 mA, VDD = 4.5V,
–40°C to +125°C
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C505
be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent nor-
mal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Does not include GP3. For GP3 see parameters D061 and D061A.
5: This spec. applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up
enabled.
6: This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit
is higher than the standard I/O logic.
DS40192C-page 62
© 1999 Microchip Technology Inc.