UT1553BBCRTMP-GPA 데이터 시트보기 (PDF) - Aeroflex UTMC
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UT1553BBCRTMP-GPA Datasheet PDF : 78 Pages
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9.0 EXCEPTION HANDLING AND
INTERRUPT LOGGING
The exception handling scheme the BCRTMP uses is based
on an interrupt structure and provides a high degree of
flexibility in:
• defining the events that cause an interrupt,
• selecting between High-Priority and Standard
interrupts, and
• selecting the amount of interrupt history retained.
The interrupt structure consists of internal registers that
enable interrupt generation, control bits in the RT and BC
data structures (see the Remote Terminal Descriptor
Definition section, page 30, and the Bus Controller
Command Block definition, page 35), and an Interrupt Log
List that sequentially stores an interrupt events record in
system memory.
The BCRTMP generates the Interrupt Log List (see figure
18) to allow the host CPU to view the Standard Interrupt
occurrences in chronological order. Each Interrupt Log List
entry contains three words. The first, the Interrupt Status
Word, indicates the type of interrupt (entries are only for
interrupts enabled). In the BC mode, the second word is a
Command Block Pointer that refers to the corresponding
Command Block. In the RT mode, the second word is a
Descriptor Pointer that refers to the corresponding
subaddress descriptor. The CPU-initialized third word, a
Tail Pointer, is read by the BCRTMP to determine the next
Interrupt Log List address. The list length can be as long or
as short as required. The configuration of the Tail Pointers
determines the list length.
The host CPU initializes the list by setting the tail pointers.
This gives flexibility in the list capacity and the ability to link
the list around noncontiguous blocks of memory. The host
CPU sets the list’s starting address using the Interrupt Log
List Register. The BCRTMP then updates this register with
the address of the next list entry.The internal High-Priority
Interrupt Status/Reset Register indicates the cause of a High-
Priority Interrupt. The High-Priority Interrupt signal is reset
by writing a “1” to the set bits in this register.
INTERRUPT LOG LIST
POINTER REGISTER
ENTRY #1
INTERRUPT STATUS
WORD
COMMAND BLOCK
POINTER
SUBADDRESS/MODE
CODE DESCRIPTOR
POINTER
TAIL POINTER
ENTRY #2
ENTRY #3
Figure 18. Interrupt Log List
The interrupt structure also uses three BCRTMP- driven
output signals to indicate when an interrupt event occurs:
STDINTL
Standard Interrupt Level. This signal is
asserted when one or more of the events
enabled in the Standard Interrupt Enable
Register occurs. Clear the signal by resetting
the Standard Interrupt bit in the High-Priority
Interrupt Status/Reset Register.
STDINTP
Standard Interrupt Pulse. This signal is
pulsed for each occurrence of an event
enabled in the Standard Interrupt
Enable Register.
HPINT
High-Priority Interrupt. This signal is
asserted for each occurrence of an event
enabled in the High-Priority Interrupt/Enable
Register. Writing to the corresponding bit in
the High-Priority Status/Reset Register
resets it.
BCRTMP-46
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