PIC16F882-I/SPQTP 데이터 시트보기 (PDF) - Microchip Technology
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PIC16F882-I/SPQTP Datasheet PDF : 338 Pages
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PIC16F882/883/884/886/887
13.3.6 SLEEP OPERATION
In Master mode, all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI transmit/receive shift register.
When all eight bits have been received, the MSSP
interrupt flag bit will be set and, if enabled, will wake the
device from Sleep.
13.3.7 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
13.3.8 BUS MODE COMPATIBILITY
Table 13-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 13-1: SPI BUS MODES
Standard SPI Mode
Terminology
Control Bits State
CKP
CKE
0, 0
0
1
0, 1
0
0
1, 0
1
1
1, 1
1
0
There is also a SMP bit that controls when the data will
be sampled.
TABLE 13-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
INTCON GIE/GIEH PEIE/GIEL T0IE INTE RBIE
T0IF
INTF
RBIF
33
PIE1
—
ADIE
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
34
PIR1
—
ADIF
RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
36
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
187
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
185
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
184
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
41
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
55
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in
SPI mode.
Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
DS41291G-page 192
2006-2012 Microchip Technology Inc.
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