FDC37B78X 데이터 시트보기 (PDF) - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

OSCILLATOR

FREQUENCY

32.768 KHz

32.768 KHz

32.768 KHz

32.768 KHz

32.768 KHz

Table 66 - Divider Selection Bits

REGISTER A BITS

DV2 DV1 DV0

MODE

0

0

0 Reset Divider

0

0

1 Reset Divider

0

1

0 Normal Operate

0

1

1 Test

1

0

X Test

1

1

X Reset Divider

Table 67 - Periodic Interrupt Rates

RATE SELECT

32.768 KHz TIME BASE

PERIOD RATE OF

FREQUENCY OF

RS3 RS2 RS1 RS0

INTERRUPT

INTERRUPT

0

0

0

0

0.0

0

0

0

1

3.90625 ms

256 Hz

0

0

1

0

7.8125 ms

128 Hz

0

0

1

1

122.070 µs

8.192 KHz

0

1

0

0

244.141 µs

4.096 KHz

0

1

0

1

488.281 µs

2.048 KHz

0

1

1

0

976.562 µs

1.024 KHz

0

1

1

1

1.953125 ms

512 Hz

1

0

0

0

3.90625 ms

256 Hz

1

0

0

1

7.8125 ms

128 Hz

1

0

1

0

15.625 ms

64 Hz

1

0

1

1

31.25 ms

32 Hz

1

1

0

0

62.5 ms

16 Hz

1

1

0

1

125 ms

8 Hz

1

1

1

0

250 ms

4 Hz

1

1

1

1

500 ms

2 Hz

REGISTER B (BH)

MSB

b7

b6

b5

b4

SET

PIE

AIE

UIE

SET

When the SET bit is a "0", the update functions

normally by advancing the counts once per

second. When the SET bit is a "1", an update

cycle in progress is aborted and the program

b3

RES

b2

DM2

b1

24/12

LSB

b0

DSE

may initialize the time and calendar bytes

without an update occurring in the middle of

initialization. SET is a read/write bit which is

not modified by RESET_DRV or any internal

functions.

143

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