FDC37B78X 데이터 시트보기 (PDF) - SMSC -> Microchip
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FDC37B78X
SMSC -> Microchip
FDC37B78X Datasheet PDF : 258 Pages
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General Purpose Event Status Register 1 (GPE_STS1)
Register Location: <PM1_BLK>+8 System I/O Space
Default Value: 00h on Vbat POR
Attribute: Read/Write (Note 0)
Size: 8-bits
BIT NAME
DESCRIPTION
0 SCI_STS1 This bit is set when the device power management events (PME events) occur.
When enabled, the setting of this bit will generate an SCI Interrupt (Note 1).
Writing a “1” to this bit will clear it if there are no pending PME events. See
Figure 5.
1-7 Reserved Reserved. These bits always return a value of zero.
Note 1: This bit is set by hardware and can only be cleared by software writing a one to this bit
position and by Vbat POR. Writing a 0 has no effect.
General Purpose Event Enable Register 1 (GPE_EN1)
Register Location: <PM1_BLK>+9 System I/O Space
Default Value: 00h on Vbat POR
Attribute: Read/Write (Note 0)
Size: 8-bits
BIT NAME
DESCRIPTION
0
SCI_EN1 When this bit is set, then the enabled device power management events (PME
events) will generate an SCI interrupt. When this bit is reset, device power
management events will not generate an SCI interrupt.
1-7 Reserved Reserved. These bits always return a value of zero.
Note 0: all bits described as "reserved" in writeable registers must be written with the value 0 when the
register is written.
PME Registers
The power management event function has a PME_Status bit and a PME_En bit. These bits are
defined in the PCI Bus Power Management Interface Specification, Revision 1.0, Draft, Copyright ©
1997, PCI Special Interest Group, Mar. 18, 1997.
The default states for the PME_Status and PME_En bits are controlled by Vbat Power-On-Reset.
PME Status Register (PME_STS)
Register Location: <PM1_BLK>+10h System I/O Space
Default Value: 00h on Vbat POR
Attribute: Read/Write (Note 0)
Size: 8-bits
D7 D6 D5 D4 D3 D2 D1
D0
DEFAULT
RESERVED
PME_Status
0x00
160
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