FDC37B78X 데이터 시트보기 (PDF) - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

PS/2 Mode

7

6

5

4

3

2

1

0

DSK

1

1

1

1 DRATE DRATE nHIGH

CHG

SEL1 SEL0 nDENS

RESET N/A N/A N/A N/A N/A N/A N/A

1

COND.

BIT 0 nHIGH DENS

This bit is low whenever the 500 Kbps or 1 Mbps

data rates are selected, and high when 250

Kbps and 300 Kbps are selected.

BITS 1 - 2 DATA RATE SELECT

These bits control the data rate of the floppy

controller. See Table 11 for the settings

corresponding to the individual data rates. The

data rate select bits are unaffected by a

software reset, and are set to 250 Kbps after a

hardware reset.

BITS 3 - 6 UNDEFINED

Always read as a logic "1"

BIT 7 DSKCHG

This bit monitors the pin of the same name and

reflects the opposite value seen on the disk

cable or the value programmed in the Force

Disk Change Register (see Configuration

Register LD8:CRC1[1:0]).

31

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