FDC37B78X 데이터 시트보기 (PDF) - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

TABLE 37 - REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL

REGISTER

REGISTER

ADDRESS*

REGISTER NAME

SYMBOL

BIT 0

BIT 1

ADDR = 0

DLAB = 0

Receive Buffer Register (Read Only)

RBR

Data Bit 0 Data Bit 1

(Note 1)

ADDR = 0

DLAB = 0

Transmitter Holding Register (Write

Only)

THR Data Bit 0 Data Bit 1

ADDR = 1

DLAB = 0

Interrupt Enable Register

IER Enable

Enable

Received Transmitter

Data

Holding

Available Register

Interrupt Empty

(ERDAI)

Interrupt

(ETHREI)

ADDR = 2

Interrupt Ident. Register (Read Only)

IIR

"0" if

Interrupt ID Bit

Interrupt

Pending

ADDR = 2

FIFO Control Register (Write Only)

FCR FIFO

(Note 7) Enable

RCVR FIFO

Reset

ADDR = 3

Line Control Register

LCR

Word

Length

Select Bit 0

(WLS0)

Word Length

Select Bit 1

(WLS1)

ADDR = 4

MODEM Control Register

MCR

Data

Terminal

Ready

(DTR)

Request to

Send (RTS)

ADDR = 5

Line Status Register

LSR Data Ready Overrun Error

(DR)

(OE)

ADDR = 6

MODEM Status Register

MSR

Delta Clear Delta Data Set

to Send

Ready

(DCTS)

(DDSR)

ADDR = 7

Scratch Register (Note 4)

SCR Bit 0

Bit 1

ADDR = 0

DLAB = 1

Divisor Latch (LS)

DDL Bit 0

Bit 1

ADDR = 1

DLAB = 1

Divisor Latch (MS)

DLM Bit 8

Bit 9

*DLAB is Bit 7 of the Line Control Register (ADDR = 3).

Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift

register is empty.

83

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