LH28F800BGE-BL12 데이터 시트보기 (PDF) - Sharp Electronics
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LH28F800BGE-BL12 Datasheet PDF : 43 Pages
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LH28F800BG-L/BGH-L (FOR TSOP, CSP)
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (NOTE 1)
• VCC = 2.7 to 3.6 V, TA = 0 to +70˚C or –40 to +85˚C
VERSIONS
LH28F800BG-L85 LH28F800BG-L12
LH28F800BGH-L85 LH28F800BGH-L12 UNIT
SYMBOL
PARAMETER
NOTE
tAVAV Write Cycle Time
tPHEL RP# High Recovery to CE# Going Low
2
tWLEL WE# Setup to CE# Going Low
tELEH CE# Pulse Width
tPHHEH RP# VHH Setup to CE# Going High
2
tSHEH WP# VIH Setup to CE# Going High
2
tVPEH VPP Setup to CE# Going High
2
tAVEH Address Setup to CE# Going High
3
tDVEH Data Setup to CE# Going High
3
tEHDX Data Hold from CE# High
tEHAX Address Hold from CE# High
tEHWH WE# Hold from CE# High
tEHEL CE# Pulse Width High
tEHRL CE# High to RY/BY# Going Low
tEHGL Write Recovery before Read
tQVVL VPP Hold from Valid SRD, RY/BY# High
2, 4
tQVPH RP# VHH Hold from Valid SRD, RY/BY# High 2, 4
tQVSL WP# VIH Hold from Valid SRD, RY/BY# High 2, 4
MIN.
120
1
0
70
100
100
100
50
50
5
5
0
25
0
0
0
0
MAX.
100
MIN.
150
1
0
70
100
100
100
50
50
5
5
0
25
0
0
0
0
MAX.
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100 ns
ns
ns
ns
ns
NOTES :
1. In systems where CE# defines the write pulse width
(within a longer WE# timing waveform), all setup, hold,
and inactive WE# times should be measured relative to
the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN and DIN for block erase or
word write.
4. VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block erase
or word write success (SR.1/3/4/5 = 0 : on Boot Blocks,
SR.3/4/5 = 0 : on Parameter Blocks and Main Blocks).
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