ST72E121J4D0 데이터 시트보기 (PDF) - STMicroelectronics

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ST72E121J4D0

8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, WDG, SCI, SPI AND 2 TIMERS

STMicroelectronics 

ST72E121 ST72T121

16-BIT TIMER (Cont’d)

4.3.3.7 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the

generation of a signal with a frequency and pulse

length determined by the value of the OC1R and

OC2R registers.

The pulse width modulation mode uses the com-

plete Output Compare 1 function plus the OC2R

register, and so these functionality can not be

used when the PWM mode is activated.

Procedure

To use pulse width modulation mode:

1. Load the OC2R register with the value corre-

sponding to the period of the signal.

2. Load the OC1R register with the value corre-

sponding to the length of the pulse if (OLVL1=0

and OLVL2=1).

3. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with OC1R register.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with OC2R register.

4. Select the following in the CR2 register:

– Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function.

– Set the PWM bit.

– Select the timer clock (CC1-CC0) (see Table

14).

If OLVL1=1 and OLVL2=0 the length of the posi-

tive pulse is the difference between the OC2R and

OC1R registers.

If OLVL1=OLVL2 a continuous signal will be seen

on the OCMP1 pin.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

OCiR Value = t * fCPU - 5

PRESC

Where:

t

= Desired output compare period (in sec-

onds)

fCPU = Internal clock frequency

PRESC = Timer prescaler factor (2, 4 or 8 de-

pending on CC1-CC0 bits, see Table

14)

The Output Compare 2 event causes the counter

to be initialized to FFFCh (See Figure 31).

Pulse Width Modulation cycle

When

Counter

= OC1R

OCMP1 = OLVL1

When

Counter

= OC2R

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 bit is set

Notes:

1. After a write instruction to the OCiHR register,

the output compare function is inhibited until the

OCiLR register is also written.

Therefore the Input Capture 1 function is inhib-

ited but the Input Capture 2 is available.

2. The OCF1 and OCF2 bits cannot be set by

hardware in PWM mode therefore the Output

Compare interrupt is inhibited.

3. The ICF1 bit is set by hardware when the coun-

ter reaches the OC2R value and can produce a

timer interrupt if the ICIE bit is set and the I bit is

cleared.

4. In PWM mode the ICAP1 pin can not be used

to perform input capture because it is discon-

nected to the timer. The ICAP2 pin can be used

to perform input capture (ICF2 can be set and

IC2R can be loaded) but the user must take

care that the counter is reset each period and

ICF1 can also generates interrupt if ICIE is set.

5. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

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